US5841722A
Expired / Lapsed
US
⏱️ 0.0 years remaining
First-in, first-out (FIFO) buffer
Assignee: Galileo Technology Ltd
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Filing: 1997-02-13
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Granted: 1998-11-24
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Expires: 2017-02-13
Abstract
Abstract A variable sized FIFO buffer whose size changes in accordance with how much data is present to be passed between the two systems is provided. One embodiment of the FIFO buffer includes at least one lower FIFO, at least one upper FIFO, a RAM and a controller. The upper FIFO buffer receives data from a first system and the lower FIFO buffer writes data to a second system. The RAM is utilized when data can no longer flow between the upper and lower FIFO buffers, due to the lower FIFO buffer being temporarily full.
Inventors
- 👤 Avigdor Willenz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 22:24
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/10
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
224 words
A variable sized, first-in, first-put (FIFO) buffer to be placed between a first and a second system, the FIFO buffer comprising: a least one upper FIFO buffer for receiving data from said first system; at least one lower FIFO buffer for writing data to said second system; a random access memory element for receiving data from said at least one upper FIFO buffer when said at least one lower FIFO buffer is temporarily full; and a controller for writing data from said at least one upper FIFO buffer to said at least one lower FIFO buffer when said at least one lower FIFO buffer is not full and into random access memory element when said at least one lower FIFO buffer is full and for reading data from said random access memory element into said at least one lower FIFO buffer when there is data in said random access memory element and said at least one lower FIFO buffer is no longer full wherein said controller includes a block generator for combining data from said at least one upper FIFO buffer into blocks for writing into said random access memory element and a block separator for separating blocks of data read from said random access memory element into separate words and for writing said separate words into said at least one lower FIFO buffer.
Claim 2
Dependent Claim
224 words
A variable sized, first-in, first-put (FIFO) buffer to be placed between a first and a second system, the FIFO buffer comprising: a least one upper FIFO buffer for receiving data from said first system; at least one lower FIFO buffer for writing data to said second system; a random access memory element for receiving data from said at least one upper FIFO buffer when said at least one lower FIFO buffer is temporarily full; and a controller for writing data from said at least one upper FIFO buffer to said at least one lower FIFO buffer when said at least one lower FIFO buffer is not full and into random access memory element when said at least one lower FIFO buffer is full and for reading data from said random access memory element into said at least one lower FIFO buffer when there is data in said random access memory element and said at least one lower FIFO buffer is no longer full wherein said controller includes a block generator for combining data from said at least one upper FIFO buffer into blocks for writing into said random access memory element and a block separator for separating blocks of data read from said random access memory element into separate words and for writing said separate words into said at least one lower FIFO buffer.
Claim 3
Dependent Claim
250 words
A buffering element to be placed between a first and a second system, the buffering element comprising: a random access memory element for storing data in a first-in, first-out manner; at least one upper FIFO buffer connected to said first system and connectable to said random access memory element; at least one lower FIFO buffer connected to said second system and connectable at least to said random access memory element; and a controller for directing data from sold first system to said second system through said upper and lower FIFO elements and said random access memory element and including a control unit for writing data from said at least one upper FIFO buffer to said at least one lower FIFO buffer when said at least one lower FIFO buffer is not full and into said random access memory element when said at least one lower FIFO buffer is full and for reading data from said random access memory element into said at least one lower FIFO buffer when there is data in said random access memory element and said at least one lower FIFO buffer is no longer full, wherein said controller includes a block generator for combining data from said at least one upper FIFO buffer into blocks for writing into said random access memory element and a block separator for separating blocks of data read from said random access memory element into separate words and for writing said separate words into said at least one lower FIFO buffer.
Claim 4
Dependent Claim
250 words
A buffering element to be placed between a first and a second system, the buffering element comprising: a random access memory element for storing data in a first-in, first-out manner; at least one upper FIFO buffer connected to said first system and connectable to said random access memory element; at least one lower FIFO buffer connected to said second system and connectable at least to said random access memory element; and a controller for directing data from sold first system to said second system through said upper and lower FIFO elements and said random access memory element and including a control unit for writing data from said at least one upper FIFO buffer to said at least one lower FIFO buffer when said at least one lower FIFO buffer is not full and into said random access memory element when said at least one lower FIFO buffer is full and for reading data from said random access memory element into said at least one lower FIFO buffer when there is data in said random access memory element and said at least one lower FIFO buffer is no longer full, wherein said controller includes a block generator for combining data from said at least one upper FIFO buffer into blocks for writing into said random access memory element and a block separator for separating blocks of data read from said random access memory element into separate words and for writing said separate words into said at least one lower FIFO buffer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-23 | 2002-05-25 | 2002-11-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-23 | 2006-05-25 | 2006-11-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-23 | 2010-05-25 | 2010-11-24 | $7700.00 | Window Closed / Lapsed |