Memory control device

Claim 2

A memory control device for controlling writing and reading of data in and from storage means including a plurality of FIFO memories, said storage means being interposed between a first function circuit and a second function circuit and capable of storing data transferred between the first and second function circuits, said memory control device comprising: writing clock generating means for generating a writing clock for writing data in the storage means based upon a specified reference clock, the reference clock being a clock for data transfer; means for applying the writing clock generated by said writing clock generating means to the plurality of FIFO memories so as to circularly write data in the plurality of FIFO memories; reading clock generating means for generating a reading clock for reading data from the storage means based upon the specified reference clock; means for applying the reading clock generated by said reading clock generating means to the plurality of FIFO memories so as to circularly read data from the plurality of FIFO memories; means for applying a writing authorizing signal commonly to the plurality of FIFO memories so as to authorize the plurality of FIFO memories to write data; means for applying a reading authorizing signal commonly to the plurality of FIFO memories so as to authorize the plurality of FIFO memories to read data; and means for organizing the relations between the reading clock and the writing clock so that in response to the writing authorizing signal the first data is written in any FIFO memory where the data is first read in response to the reading authorizing signal.

Claim 3

The memory control device according to claim 1 wherein the storage means is a line memory having a capacity sufficient to store a single line of image data corresponding to a single scanning line in optically scanning and reading an original sheet.

Claim 4

The memory control device according to claim 2 wherein the first and second function circuits perform specified image processing functions, respectively.

Claim 5

A memory control device according to claim 3, wherein the first function circuit is reset at specified time intervals in accordance with a specified reset signal and saves data in the storage means for a period when the first function circuit is reset.

Claim 6

The memory control device according to claim 4, wherein the reading authorizing signal is output at a specified timing related to the reset signal.

Claim 7

The memory control device according to claim 5, further comprising: writing signal generating means for delaying the reading authorizing signal by a time corresponding to time spent for data processing by the first function circuit so as to output the delayed signal as a writing signal to the storage means.

Claim 8

A memory control device for controlling writing and reading of data in and from storage means including a plurality of FIFO memories, said memory control device comprising: writing clock generating means for generating writing clocks for writing data in the storage means based upon a specified reference clock, said writing clock generating means including means for generating writing clocks different in timing from each other and equivalent in number to the number of FIFO memories constituting the storage means; means for allocating and applying the writing clocks generated by said writing clock generating means to the plurality of FIFO memories so as to circularly write data in the plurality of FIFO memories; reading clock generating means for generating a reading clock for reading data from the storage means based upon the specified reference clock; and means for applying the reading clock generated by said reading clock generating means to the plurality of FIFO memories so as to circularly read data from the plurality of FIFO memories.

Claim 9

A memory control device for controlling writing and reading of data in and from storage means including a plurality of FIFO memories, said memory control device comprising: writing clock generating means for generating writing clocks for writing data in the storage means based upon a specified reference clock, said writing clock generating means including means for generating writing clocks different in timing from each other and equivalent in number to the number of FIFO memories constituting the storage means; means for allocating and applying the writing clocks generated by said writing clock generating means to the plurality of FIFO memories so as to circularly write data in the plurality of FIFO memories; reading clock generating means for generating a reading clock for reading data from the storage means based upon the specified reference clock; and means for applying the reading clock generated by said reading clock generating means to the plurality of FIFO memories so as to circularly read data from the plurality of FIFO memories.

Claim 10

A memory control device for controlling writing and reading of data in and from storage means including a plurality of FIFO memories, said memory control device comprising: writing clock generating means for generating a writing clock for writing data in the storage means based upon a specified reference clock; means for applying the writing clock generated by said writing clock generating means to the plurality of FIFO memories so as to circularly write data in the plurality of FIFO memories; reading clock generating means for generating reading clocks for reading data from the storage means based upon the specified reference clock, said reading clock generating means including means for generating reading clocks different in timing from each other and equivalent in number to the number of FIFO memories constituting the storage means; and means for allocating and applying the reading clocks generated by said reading clock generating means to the plurality of FIFO memories so as to circularly read data from the plurality of FIFO memories.

Claim 11

A memory control device for controlling writing and reading of data in and from storage means including a plurality of FIFO memories, said memory control device comprising: writing clock generating means for generating a writing clock for writing data in the storage means based upon a specified reference clock; means for applying the writing clock generated by said writing clock generating means to the plurality of FIFO memories so as to circularly write data in the plurality of FIFO memories; reading clock generating means for generating reading clocks for reading data from the storage means based upon the specified reference clock, said reading clock generating means including means for generating reading clocks different in timing from each other and equivalent in number to the number of FIFO memories constituting the storage means; and means for allocating and applying the reading clocks generated by said reading clock generating means to the plurality of FIFO memories so as to circularly read data from the plurality of FIFO memories.

Claim 12

A memory control device for controlling writing and reading of data in and from storage means including a plurality of FIFO memories, said memory control device comprising: writing clock generating means for generating a writing clock for writing data in the storage means based upon a specified reference clock; means for applying the writing clock generated by said writing clock generating means to the plurality of FIFO memories so as to circularly write data in the plurality of FIFO memories; reading clock generating means for generating a reading clock for reading data from the storage means based upon the specified reference clock; means for applying the reading clock generated by said reading clock generating means to the plurality of FIFO memories so as to circularly read data from the plurality of FIFO memories; and a common clock generating means shared by said writing clock generating means and said reading clock generating means, said common clock generating means generating a plurality of clocks different in timing from each other and equivalent in number to the number of FIFO memories constituting the storage means.

Claim 13

A memory control device for controlling writing and reading of data in and from storage means including a plurality of FIFO memories, said memory control device comprising: writing clock generating means for generating a writing clock for writing data in the storage means based upon a specified reference clock; means for applying the writing clock generated by said writing clock generating means to the plurality of FIFO memories so as to circularly write data in the plurality of FIFO memories; reading clock generating means for generating a reading clock for reading data from the storage means based upon the specified reference clock; means for applying the reading clock generated by said reading clock generating means to the plurality of FIFO memories so as to circularly read data from the plurality of FIFO memories; and a common clock generating means shared by said writing clock generating means and said reading clock generating means, said common clock generating means generating a plurality of clocks different in timing from each other and equivalent in number to the number of FIFO memories constituting the storage means.

Claim 14

The memory control device according to claim 9, wherein: the storage means includes three FIFO memories; said common clock generating means includes: (a) a shift register of parallel output type having a plurality of stages and a data input terminal for shifting data among stages based upon the reference clock, an output signal from a first stage turning to a specified logic status when the data input terminal turns to a specified logic status; (b) an AND circuit receiving output signals from first and second stages of said shift register and having its output applied to the data input terminal of said shift register; (c) first latch means for latching the output signal from the first stage of said shift register based upon the reference clock; (d) second latch means for latching the output from the first latch means based upon the reference clock; and (e) third latch means for latching the output from the second latch means based upon the reference clock; and said memory control device further comprises means allocating and applying signals corresponding to the output signals from the first, second and third latch means as writing clocks to the three FIFO memories, and means allocating and applying signals corresponding to the output signals from the first, second and third latch means as reading clocks to the three FIFO memories.

Claim 15

A memory control device for controlling writing and reading of data in and from storage means including a plurality of FIFO memories, said storage means being interposed between a first function circuit and a second function circuit and capable of storing data transferred between the first and second function circuits, said memory control device comprising: writing clock generating means for generating writing clocks different in timing from each other and equivalent in number to the number of FIFO memories constituting the storage means, based upon a specified reference clock; means for allocating and applying the plurality of writing clocks generated by said writing clock generating means to the plurality of FIFO memories so as to circularly write data in the plurality of FIFO memories; reading clock generating means for generating reading clocks different in timing from each other and equivalent in number to the number of FIFO memories constituting the storage means, based upon said reference clock; means for allocating and applying the plurality of reading clocks generated by said reading clock generating means to the plurality of FIFO memories so as to circularly read data from the plurality of FIFO memories; means for applying a writing authorizing signal commonly to the plurality of FIFO memories so as to authorize the plurality of FIFO memories to write data; means for applying a reading authorizing signal commonly to the plurality of FIFO memories so as to authorize the plurality of FIFO memories to read data; and means for organizing the relations between the reading clocks and the writing clocks so that in response to the writing authorizing signal the first data is written in any FIFO memory where the data is first read in response to the reading authorizing signal.

Claim 16

A memory control device for controlling writing and reading of data in and from storage means including a plurality of FIFO memories, said storage means being interposed between a first function circuit and a second function circuit and capable of storing data transferred between the first and second function circuits, said memory control device comprising: writing clock generating means for generating writing clocks different in timing from each other and equivalent in number to the number of FIFO memories constituting the storage means, based upon a specified reference clock; means for allocating and applying the plurality of writing clocks generated by said writing clock generating means to the plurality of FIFO memories so as to circularly write data in the plurality of FIFO memories; reading clock generating means for generating reading clocks different in timing from each other and equivalent in number to the number of FIFO memories constituting the storage means, based upon said reference clock; means for allocating and applying the plurality of reading clocks generated by said reading clock generating means to the plurality of FIFO memories so as to circularly read data from the plurality of FIFO memories; means for applying a writing authorizing signal commonly to the plurality of FIFO memories so as to authorize the plurality of FIFO memories to write data; means for applying a reading authorizing signal commonly to the plurality of FIFO memories so as to authorize the plurality of FIFO memories to read data; and means for organizing the relations between the reading clocks and the writing clocks so that in response to the writing authorizing signal the first data is written in any FIFO memory where the data is first read in response to the reading authorizing signal.

Claim 17

The memory control device according to claim 11, wherein the storage means is a line memory having a capacity sufficient to store a single line of image data corresponding to a single scanning line in optically scanning and reading an original sheet.

Claim 18

The memory control device according to claim 12, wherein the first and second function circuits perform respective specified image processing functions.

Claim 19

The memory control device according to claim 13, wherein the first function circuit is reset at specified time intervals in accordance with a specified reset signal and saves data in the storage means for a period when the first function circuit is reset.

Claim 20

The memory control device according to claim 14 wherein the reading authorizing signal is output at a specified timing related to the reset signal.

Claim 21

The memory control device according to claim 15, further comprising: writing signal generating means for delaying the reading authorizing signal by a time corresponding to time spent for data processing by the first function circuit so as to output the delayed signal as a writing signal to the storage means.

Claim 22

A memory control device for controlling writing and reading of data in and from storage means including a plurality of FIFO memories, said memory control device comprising: writing clock generating means for generating writing clocks different in timing from each other and equivalent in number to the number of FIFO memories constituting the storage means, based upon a specified reference clock; means for allocating and applying the plurality of writing clocks generated by said writing clock generating means to the plurality of FIFO memories so as to circularly write data in the plurality of FIFO memories; reading clock generating means for generating reading clocks different in timing from each other and equivalent in number of the number of FIFO memories constituting the storage means, based upon said reference clock; means for allocating and applying the plurality of reading clocks generated by said reading clock generating means to the plurality of FIFO memories so as to circularly read data from the plurality of FIFO memories; and a common clock generating means shared by said writing clock generating means and said reading clock generating means, said common clock generating means generating a plurality of clocks different in timing from each other and equivalent in number to the number of FIFO memories constituting the storage means.

Claim 23

A memory control device for controlling writing and reading of data in and from storage means including a plurality of FIFO memories, said memory control device comprising: writing clock generating means for generating writing clocks different in timing from each other and equivalent in number to the number of FIFO memories constituting the storage means, based upon a specified reference clock; means for allocating and applying the plurality of writing clocks generated by said writing clock generating means to the plurality of FIFO memories so as to circularly write data in the plurality of FIFO memories; reading clock generating means for generating reading clocks different in timing from each other and equivalent in number of the number of FIFO memories constituting the storage means, based upon said reference clock; means for allocating and applying the plurality of reading clocks generated by said reading clock generating means to the plurality of FIFO memories so as to circularly read data from the plurality of FIFO memories; and a common clock generating means shared by said writing clock generating means and said reading clock generating means, said common clock generating means generating a plurality of clocks different in timing from each other and equivalent in number to the number of FIFO memories constituting the storage means.

Claim 24

The memory control according to claim 17, wherein: the storage means includes three FIFO memories; said clock generating means includes: (a) a shift register of parallel output type having a plurality of stages and a data input terminal for shifting data among stages based upon the reference clock, an output signal from a first stage turning to a specified logic status when the data input terminal turns to a specified logic status, (b) an AND circuit receiving output signal from first and second stages of said shift register and having its output applied to the data input terminal of said shift register, (c) first latch means for latching an output signal from the first stage of said shift register based upon the reference clock, (d) second latch means for latching the output from the first latch means based upon the reference clock, and (e) third latch means for latching the output from the second latch means based upon the reference clock; means allocating and applying signals corresponding to the output signals from the first, second and third latch means as writing clocks to the three FIFO memories; and means allocating and applying signals corresponding to the output signals from the first, second and third latch means as reading clocks to the three FIFO memories.

Claim 25

A memory control device for controlling writing and reading of data in and from a plurality of storage means, wherein each storage means is interposed between a pair of function circuits connected in series, and wherein each storage means includes a plurality of FIFO memories, said memory control device comprising: writing clock generating means for generating a writing clock to be applied commonly to the plurality of storage means based upon a specified reference clock so as to write data in the plurality of storage means; means for applying the writing clock generated by said writing clock generating means to the plurality of FIFO memories of each storage means so as to circularly write data in the plurality of FIFO memories of each storage means; reading clock generating means for generating a reading clock to be applied commonly to the plurality of storage means based upon the specified reference clock so as to read stored data from the plurality of storage means; and means for applying the reading clock generated by said reading clock generating means to the plurality of FIFO memories of each storage means so as to circularly read data from the plurality of FIFO memories of each storage means.

Claim 26

A memory control device for controlling writing and reading of data in and from a plurality of storage means, wherein each storage means is interposed between a pair of function circuits connected in series, and wherein each storage means includes a plurality of FIFO memories, said memory control device comprising: writing clock generating means for generating a writing clock to be applied commonly to the plurality of storage means based upon a specified reference clock so as to write data in the plurality of storage means; means for applying the writing clock generated by said writing clock generating means to the plurality of FIFO memories of each storage means so as to circularly write data in the plurality of FIFO memories of each storage means; reading clock generating means for generating a reading clock to be applied commonly to the plurality of storage means based upon the specified reference clock so as to read stored data from the plurality of storage means; and means for applying the reading clock generated by said reading clock generating means to the plurality of FIFO memories of each storage means so as to circularly read data from the plurality of FIFO memories of each storage means.

Claim 27

The memory control device according to claim 19, further comprising means for applying a writing authorizing signal commonly to the plurality of FIFO memories of each storage means to authorize the plurality of FIFO memories to write data; means for applying a reading authorizing signal commonly to the plurality of FIFO memories of each storage means to authorize the plurality of FIFO memories to read data; and means for organizing the relations between the reading clock and the writing clock in each storage means so that in response to the writing authorizing signal the first data is written in any FIFO memory where data is first read in response to the reading authorizing signal.

Claim 28

The memory control device according to claim 20, wherein: the storage means are capable of storing data transferred between the function circuits; and the reference clock is a clock for data transfer.

Claim 29

The memory control device according to claim 21, wherein the plurality of storage means are line memories, each line memory having a capacity sufficient to store a single line of image data corresponding to a single scanning line in optically scanning and reading an original sheet.

Claim 30

The memory control device according to claim 22, wherein the plurality of function circuits perform respective specified image processing functions.

Claim 31

The memory control device according to claim 23, wherein each of the function circuits is reset at specified time intervals in accordance with a specified reset signal and saves data into the storage means interposed between such function circuit and another function circuit for a period when such function circuit is reset.

Claim 32

The memory control device according to claim 24, wherein the reading authorizing signal is output at a specified timing related to the reset signal.

Claim 33

The memory control device according to claim 25, further comprising for each function circuit, writing signal generating means for delaying the reading authorizing signal by a time corresponding to time spent for data processing in each function circuit so as to output the delayed signal as a writing signal to the storage means interposed between such function circuit and another function circuit.

Claim 34

The memory control device according to claim 19, wherein said writing clock generating means includes means for generating writing clocks different in timing from each other and equivalent in number to the number of FIFO memories constituting each storage means, and means for allocating and assigning the writing clocks to the plurality of FIFO memories constituting each storage means.

Claim 35

The memory control device according to claim 19, wherein said reading clock generating means includes means for generating reading clocks different in timing from each other and equivalent in number to the number of FIFO memories constituting each storage means, and means for allocating and assigning the reading clocks to the plurality of FIFO memories constituting each storage means.

Claim 36

The memory control device according to claim 19, further comprising a common clock generating means shared by said writing clock generating means and said reading clock generating means, said common clock generating means generating a plurality of clocks different in timing from each other and equivalent in number to the number of FIFO memories constituting each storage means.

Claim 37

The memory control device according to claim 29, wherein: each storage means includes three FIFO memories; said clock generating means includes: (a) a shift register of parallel output type having a plurality of stages and a data input terminal for shifting data among stages based upon the reference clock, an output signal from a first stage turning to a specified logic status when the data input terminal turns to a specified logic status, (b) an AND circuit receiving output signal from first and second stages of said shift register and having its output applied to the data input terminal of said shift register, (c) first latch means for latching an output signal from the first stage of said shift register based upon the reference clock, (d) second latch means for latching the output from the first latch means based upon the reference clock, and (e) third latch means for latching the output from the second latch means based upon the reference clock; and said memory control device further comprises means allocating and assigning signals corresponding to output signals from said first, second and third latch means as writing clocks to the three FIFO memories constituting each storage means, and means allocating and assigning signals corresponding to output signals from said first, second and third latch means as writing clocks to the three FIFO memories constituting each storage means.

Claim 38

The memory control device according to claim 19, further comprising means for applying a reading authorizing signal, for reading data at a common timing, to said plurality of storage means.