US5841672A
Expired / Lapsed
US
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Method and apparatus for verifying signal timing of electrical circuits
Assignee: Philips Semiconductors Inc
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Filing: 1996-02-13
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Granted: 1998-11-24
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Expires: 2016-02-13
Abstract
Abstract The present invention is directed to a method and apparatus for accurately estimating signal delays of an electrical circuit by taking into account both resistance and capacitance of an interconnect network when determining both gate delays and interconnect delays of the circuit. Exemplary embodiments of the present invention, by providing a highly accurate estimate of signal delays, result in highly efficient, cost-effective electrical circuit design and fabrication. Further, a high degree of customer satisfaction can be realized because the possibility that a given electrical circuit will not comply with customer specified time constraints is minimal.
Inventors
- 👤 Athanasius W. Spyrou
- 👤 Michael Grossman
- 👤 Michael Misheloff
- 👤 Thomas Schaefer
- 👤 Marie C. Salet
- 👤 Clementina Bures
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 03:35
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
117 words
A method of verifying operation of an electrical circuit comprising the steps of: producing an electrical circuit having at least one gate and an output network connected with the gate; obtaining an estimated total gate delay and an estimated gate output slew time of the gate using a gate timing model; producing a differential estimated output network delay as a function of output network resistance and estimated gate driving strength for a destination point of the output network; combining the estimated total gate delay and the estimated output network delay to produce a combined delay from an input of the gate to said destination point; and using said combined delay to verify operation of said electrical circuit.
Claim 2
Independent Claim
117 words
A method of verifying operation of an electrical circuit comprising the steps of: producing an electrical circuit having at least one gate and an output network connected with the gate; obtaining an estimated total gate delay and an estimated gate output slew time of the gate using a gate timing model; producing a differential estimated output network delay as a function of output network resistance and estimated gate driving strength for a destination point of the output network; combining the estimated total gate delay and the estimated output network delay to produce a combined delay from an input of the gate to said destination point; and using said combined delay to verify operation of said electrical circuit.
Claim 3
Dependent Claim
27 words
A method according to claim 1, wherein said estimated gate driving strength is a ramp factor which is a function of said estimated gate output slew time.
Claim 4
Dependent Claim
27 words
A method according to claim 2, wherein said ramp factor is obtained by dividing said estimated gate output slew time by a load of said output network.
Claim 5
Dependent Claim
17 words
A method according to claim 1, wherein said load is a capacitive load of said output network.
Claim 6
Dependent Claim
46 words
A method according to claim 1, wherein said step of producing a differential estimated output network delay as a function of output network resistance is performed for each of a plurality of destination points, each of said destination points representing an input to a subsequent gate.
Claim 7
Dependent Claim
34 words
A method according to claim 5, wherein said step of combining the estimated total gate delay and the differential estimated output network delay is performed separately for each of said plurality of destination points.
Claim 8
Dependent Claim
34 words
A method according to claim 1, wherein said step of combining the estimated total gate delay and the differential estimated output network delay is performed separately for each of a plurality of destination points.
Claim 9
Dependent Claim
75 words
A method according to claim 1, wherein said step of producing a differential estimated output network delay further includes the steps of: determining a first interconnect delay as a function of the resistance and capacitance of the output network; determining a second interconnect delay as a function of the capacitance of the output network; and determining said differential estimated output network delay as the difference between said first interconnect delay and said second interconnect delay.
Claim 10
Dependent Claim
41 words
A method according to claim 1, further comprising a step of: combining the differential estimated output network delay and the estimated gate output slew time to produce an estimated destination point slew time at said destination point of the output network.
Claim 11
Dependent Claim
58 words
A method according to claim 1, wherein said step of obtaining further includes the step of: establishing said gate timing model as a function of timing parameter values for the gate, as a function of an input slew time of an input signal to the gate, and as a function of total non-resistive load of the output network.
Claim 12
Dependent Claim
50 words
A method according to claim 9, wherein said steps of combining the estimated total gate delay and the differential estimated output network delay, and the step of combining the differential estimated output network delay and the estimated gate output slew time are repeated iteratively until a threshold convergence is achieved.
Claim 13
Independent Claim
121 words
A method of verifying operation of an electrical circuit comprising the steps of: producing an electrical circuit having at least one gate and an output network connected with the gate; obtaining an estimated total gate delay and an estimated gate output slew time of the gate using a gate timing model; producing an estimated output network delay as a function of output network resistance and estimated gate driving strength for a destination point of the output network; combining the estimated output network delay and the estimated gate output slew time to produce an estimated destination point slew time at said destination point of the output network; and using said estimated destination point slew time to verify operation of said electrical circuit.
Claim 14
Independent Claim
121 words
A method of verifying operation of an electrical circuit comprising the steps of: producing an electrical circuit having at least one gate and an output network connected with the gate; obtaining an estimated total gate delay and an estimated gate output slew time of the gate using a gate timing model; producing an estimated output network delay as a function of output network resistance and estimated gate driving strength for a destination point of the output network; combining the estimated output network delay and the estimated gate output slew time to produce an estimated destination point slew time at said destination point of the output network; and using said estimated destination point slew time to verify operation of said electrical circuit.
Claim 15
Dependent Claim
27 words
A method according to claim 12, wherein said estimated gate driving strength is a ramp factor which is a function of said estimated gate output slew time.
Claim 16
Dependent Claim
27 words
A method according to claim 13, wherein said ramp factor is obtained by dividing said estimated gate output slew time by a load of said output network.
Claim 17
Dependent Claim
17 words
A method according to claim 14, wherein said load is a capacitive load of said output network.
Claim 18
Independent Claim
116 words
An apparatus for verifying operation of an electrical circuit comprising: means for producing an electrical circuit having at least one gate and an output network connected with the gate, said gate having an estimated total gate delay and a differential estimated gate output slew time; means for producing an estimated output network delay as a function of output network resistance and estimated gate driving strength for a destination point of the output network; and means for processing the estimated total gate delay and the estimated output network delay to produce a combined delay from an input of the gate to said destination point, and for using said combined delay to verify operation of said electrical circuit.
Claim 19
Independent Claim
116 words
An apparatus for verifying operation of an electrical circuit comprising: means for producing an electrical circuit having at least one gate and an output network connected with the gate, said gate having an estimated total gate delay and a differential estimated gate output slew time; means for producing an estimated output network delay as a function of output network resistance and estimated gate driving strength for a destination point of the output network; and means for processing the estimated total gate delay and the estimated output network delay to produce a combined delay from an input of the gate to said destination point, and for using said combined delay to verify operation of said electrical circuit.
Claim 20
Dependent Claim
37 words
An apparatus according to claim 16, wherein said means for processing further combines the estimated output network delay and the estimated gate output slew time to produce an estimated destination point slew time at said destination point.
Claim 21
Independent Claim
97 words
An apparatus for verifying operation of an electrical circuit comprising: a strength sensitive resistance-capacitance delay calculator for producing a differential estimated output network delay as a function of output network resistance and estimated gate driving strength for a destination point of the output network; and a processor for combining an estimated total gate delay of at least one gate in an electrical circuit with the differential estimated output network delay to produce a combined delay from an input of the gate to said destination, and for using said combined delay to verify operation of said electrical circuit.
Claim 22
Independent Claim
97 words
An apparatus for verifying operation of an electrical circuit comprising: a strength sensitive resistance-capacitance delay calculator for producing a differential estimated output network delay as a function of output network resistance and estimated gate driving strength for a destination point of the output network; and a processor for combining an estimated total gate delay of at least one gate in an electrical circuit with the differential estimated output network delay to produce a combined delay from an input of the gate to said destination, and for using said combined delay to verify operation of said electrical circuit.
Claim 23
Dependent Claim
39 words
Apparatus according to claim 18, wherein said processor further combines the differential estimated output network delay and an estimated gate output slew time to produce an estimated destination point slew time at said destination point of the output network.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-23 | 2002-05-25 | 2002-11-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-23 | 2006-05-25 | 2006-11-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-23 | 2010-05-25 | 2010-11-24 | $7700.00 | Window Closed / Lapsed |