Patent US5841315A successfully refreshed from Google Patents.
US5841315A
Expired / Lapsed
US
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Matched filter circuit
Assignee: Yozan Inc
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Filing: 1996-07-26
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Granted: 1998-11-24
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Expires: 2016-07-26
Abstract
Abstract An object of the present invention is to provide a matched filter circuit of small size and consuming low electric power. Paying attention that a spreading code is a 1 bit data string, an input signal is sampled and held as an analog signal along the time sequence, classified into "1" and "-1" and the classified signals are added in parallel by capacitive coupling in a matched filter circuit according to the present invention.
Inventors
- 👤 Guoliang Shou
- 👤 Changming Zhou
- 👤 Kazunori Motohashi
- 👤 Xiaoling Qin
- 👤 Shengmin Lin
- 👤 Makoto Yamamoto
- 👤 Sunao Takatori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:43
CPC Classifications
H; H03; H03L; H03L7/00; H04; H04B; H04B1/00; H04B1/69; H04B1/707; H04B1/709; H04B1/7093; H03H; H03H11/00; H03H11/02; H03H11/04; H03H17/00; H03H17/02; H03H17/0248; H03H17/0254; H04B1/7097; H04B1/711; H04B1/7115; H04B1/7117
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
381 words
A matched filter circuit comprising: I) a plurality of sampling and holding circuits, each sampling and holding circuit comprising: i) a switch being connected to an input voltage, ii) a first capacitance being connected to an output portion of said switch, iii) a first inverted amplifying portion including an odd number of stages of MOS inverters and being connected to said first capacitance, iv) a first feedback capacitance connecting an output portion of said first inverted amplifying portion to its input portion, v) a first multiplexer receiving an output of said first inverted amplifying portion and a reference voltage and alternatively outputting said received signals, and vi) a second multiplexer receiving said output of said first inverted amplifying portion and said reference voltage and alternatively outputting said received signals opposite to said output from said first multiplexer; II) a plurality of first addition portions, each first addition portion comprising: i) a plurality of second capacitances, each second capacitance being connected to an output portion of said first multiplexer of a corresponding sampling and holding circuit, and output portions of said second capacitances being connected with one another to form a common output, ii) a second inverted amplifying portion including odd number of stages of MOS inverters and being connected to said common output of said second capacitances, and iii) a second feedback capacitance connecting an output portion of said second inverted amplifying portion to its input portion; III) a plurality of second addition portions, each second addition portion comprising: i) a plurality of third capacitances each third capacitance being connected to an output portion of siad second multiplexer of a corresponding sampling and holding circuit, and output portions of said capacitances being connected with one another to form a common output, ii) a third inverted amplifying portion having odd number of stages of MOS inverters and being connected to said common output of said third capacitances, and iii) a third feedback capacitance connecting an output portion of said third inverted amplifying portion to its input portion; and IV) a control circuit for closing said switch of one of said sampling and holding circuits, opening said switches of other said sampling and holding circuits, and switching said first and second multiplexer of each said sampling and holding circuit by a predetermined combination.
Claim 2
Dependent Claim
381 words
A matched filter circuit comprising: I) a plurality of sampling and holding circuits, each sampling and holding circuit comprising: i) a switch being connected to an input voltage, ii) a first capacitance being connected to an output portion of said switch, iii) a first inverted amplifying portion including an odd number of stages of MOS inverters and being connected to said first capacitance, iv) a first feedback capacitance connecting an output portion of said first inverted amplifying portion to its input portion, v) a first multiplexer receiving an output of said first inverted amplifying portion and a reference voltage and alternatively outputting said received signals, and vi) a second multiplexer receiving said output of said first inverted amplifying portion and said reference voltage and alternatively outputting said received signals opposite to said output from said first multiplexer; II) a plurality of first addition portions, each first addition portion comprising: i) a plurality of second capacitances, each second capacitance being connected to an output portion of said first multiplexer of a corresponding sampling and holding circuit, and output portions of said second capacitances being connected with one another to form a common output, ii) a second inverted amplifying portion including odd number of stages of MOS inverters and being connected to said common output of said second capacitances, and iii) a second feedback capacitance connecting an output portion of said second inverted amplifying portion to its input portion; III) a plurality of second addition portions, each second addition portion comprising: i) a plurality of third capacitances each third capacitance being connected to an output portion of siad second multiplexer of a corresponding sampling and holding circuit, and output portions of said capacitances being connected with one another to form a common output, ii) a third inverted amplifying portion having odd number of stages of MOS inverters and being connected to said common output of said third capacitances, and iii) a third feedback capacitance connecting an output portion of said third inverted amplifying portion to its input portion; and IV) a control circuit for closing said switch of one of said sampling and holding circuits, opening said switches of other said sampling and holding circuits, and switching said first and second multiplexer of each said sampling and holding circuit by a predetermined combination.
Claim 3
Dependent Claim
209 words
A matched filter circuit as claimed in claim 1, wherein said sampling and holding circuits are divided into a plurality of groups, each group including at least one each of said first and second addition portions and further comprising: a) a fourth addition portion being connected to output portions of said first addition portions of all of said groups, said fourth addition portion comprising a plurality of fourth capacitances, each fourth capacitance being connected with one of said output portion of said first addition portion, a fourth inverted amplifying portion having odd stages of MOS inverters commonly receiving said outputs of said fourth capacitances and a fourth feedback capacitance connecting an output portion of said fourth inverted amplifying portion to its input portion, and b) a fifth addition portion being connected to output portions of each of second addition portion of all of said groups, said fifth addition portion comprising a plurality of fifth capacitances, each fifth capacitance being connected with one of said output portion of said second addition portion, a fifth inverted amplifying portion having odd stages of MOS inverters commonly receiving said outputs of said fifth capacitances and a fifth feedback capacitance connecting an output portion of said fifth inverted amplifying portion to its input portion.
Claim 4
Dependent Claim
45 words
A matched filter circuit as claimed in claim 1, wherein said reference voltage is generated by a reference voltage generating circuit comprising a sixth inverted amplifying portion, and a sixth feedback connecting an output portion of said sixth inverted amplifying portion to its input portion.
Claim 5
Dependent Claim
76 words
A matched filter circuit as claimed in claims 1, 2 or 3, wherein each inverted amplifying portion further comprises a grounded capacitance between said output portion of each inverted amplifying portion and the ground, and a pair of balancing resistances being connected at an output portion of said MOS inverters other than an output portion of a last stage MOS inverter, a supply voltage and the ground being connected to one of said balancing resistance, respectively.
Claim 6
Dependent Claim
38 words
A matched filter circuit claimed in claim 3, wherein a threshold voltage of each of said MOS inverters of said sixth inverted amplifying portion is adjusted to set said reference voltage to the 1/2 of the supply voltage.
Claim 7
Dependent Claim
37 words
A matched filter circuit as claimed in claim 1, wherein said control circuit controls said sampling and holding circuits so as to hold said input voltage by said sampling and holding circuits circulatingly in a predetermined order.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-23 | 2002-05-25 | 2002-11-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-23 | 2006-05-25 | 2006-11-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-23 | 2010-05-25 | 2010-11-24 | $7700.00 | Window Closed / Lapsed |