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US5840606A
Expired / Lapsed
US
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Method for manufacturing a comb-shaped lower electrode for a DRAM capacitor
Assignee: United Microelectronics Corp
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Filing: 1997-11-25
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Granted: 1998-11-24
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Expires: 2017-11-25
Abstract
Abstract A method for manufacturing a comb-shaped lower electrode for a DRAM capacitor including the steps of providing a substrate having a transistor and an insulating layer formed thereon, wherein the insulating layer contains a contact window opening exposing a source/drain region of the transistor; then, forming a polysilicon layer over the insulating layer, the contact window opening and the exposed source/drain region; next, forming a hemispherical grain silicon over the polysilicon layer. Thereafter, an oxide layer is formed over the hemispherical grain silicon, and then a silicon nitride layer is formed over the gaps between the hemispherical grain silicon exposing portions of the oxide layer. In the subsequent step, a plurality of hard mask layers are formed over the oxide layer not covered by the silicon nitride layer, and finally the silicon nitride layer, the oxide layer and portions of the polysilicon layer are removed using the hard mask layers to form a plurality of trenches.
Inventors
- 👤 Claymens Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:44
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/043; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/716
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
140 words
A method for manufacturing a DRAM capacitor comprising the steps of: providing a substrate having a transistor and an insulating layer formed thereon, wherein the insulating layer contains a contact window opening exposing a source/drain region of the transistor; forming a polysilicon layer over the insulating layer, the contact window opening and the exposed source/drain region; forming a hemispherical grain silicon over the polysilicon layer; forming an oxide layer over the hemispherical grain silicon; forming a silicon nitride layer over gaps between the hemispherical grain silicon exposing portions of the oxide layer; forming a plurality of hard mask layers over the oxide layer not covered by the silicon nitride layer; and removing the silicon nitride layer, the oxide layer and portions of the polysilicon layer below the oxide layer using the hard mask layers to form a plurality of trenches.
Claim 2
Independent Claim
140 words
A method for manufacturing a DRAM capacitor comprising the steps of: providing a substrate having a transistor and an insulating layer formed thereon, wherein the insulating layer contains a contact window opening exposing a source/drain region of the transistor; forming a polysilicon layer over the insulating layer, the contact window opening and the exposed source/drain region; forming a hemispherical grain silicon over the polysilicon layer; forming an oxide layer over the hemispherical grain silicon; forming a silicon nitride layer over gaps between the hemispherical grain silicon exposing portions of the oxide layer; forming a plurality of hard mask layers over the oxide layer not covered by the silicon nitride layer; and removing the silicon nitride layer, the oxide layer and portions of the polysilicon layer below the oxide layer using the hard mask layers to form a plurality of trenches.
Claim 3
Dependent Claim
22 words
The method of claim 1, wherein the step of forming the polysilicon layer includes using a low pressure chemical vapor deposition method.
Claim 4
Dependent Claim
24 words
The method of claim 1, wherein the step of forming the oxide layer includes passing gaseous oxygen into an oxidation furnace for a reaction.
Claim 5
Dependent Claim
41 words
The method of claim 1, wherein the step of forming the silicon nitride layer includes the substeps of: depositing a silicon nitride material over the oxide layer; and removing portions of the silicon nitride material to form the silicon nitride layer.
Claim 6
Dependent Claim
22 words
The method of claim 4, wherein the substep of depositing the silicon nitride includes using a low pressure chemical vapor deposition method.
Claim 7
Dependent Claim
23 words
The method of claim 4, wherein the substep of removing portions of the silicon nitride material includes using a reactive ion etching method.
Claim 8
Dependent Claim
20 words
The method of claim 1, wherein the step of forming the hard mask layers includes using a wet oxidation method.
Claim 9
Dependent Claim
20 words
The method of claim 1, wherein the step of forming the trenches includes using a selective reactive ion etching method.
References Cited (Backward Citations)
US5670405A
Cited
US5670407A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-23 | 2002-05-25 | 2002-11-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-23 | 2006-05-25 | 2006-11-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-23 | 2010-05-25 | 2010-11-24 | $7700.00 | Window Closed / Lapsed |