Abstract An improved CPU for preventing a program malfunction which is capable of preventing a malfunction of a program by resetting the CPU when an abnormal data is fetched from a memory due to a noise, which includes a program counter for designating an address of an instruction to be executed, a first instruction register for storing an instruction outputted from a memory by the program counter, a second instruction register for fetching an instruction stored in the first instruction register in accordance with a first internal clock signal, a third instruction register for fetching an instruction stored in the first instruction register in accordance with a second internal clock signal, a comparator, which is operated in accordance with an enable signal, for comparing whether instructions stored in the second instruction register and the third instruction register are identical, a reset controller for outputting a reset signal in accordance with an output signal from the comparator, an instruction decoder for decoding an operation code of an instruction stored in the third instruction register in accordance with an output signal from the comparator and for outputting a control signal and a program count value change instruction, and an execution unit for executing an instruction in accordance with a control signal from the instruction decoder.
A central processing unit for preventing a program malfunction, comprising: a program counter for designating an address of an instruction to be executed; a first instruction register for storing an instruction outputted from a memory by the program counter; a second instruction register for fetching an instruction stored in the first instruction register in accordance with a first internal clock signal; a third instruction register for fetching an instruction stored in the first instruction register in accordance with a second internal clock signal; a comparator, which is operated in accordance with an enable signal, for comparing whether instructions stored in the second instruction register and the third instruction register are identical; a reset controller for outputting a reset signal in accordance with an output signal from the comparator; an instruction decoder for decoding an operation code of an instruction stored in the third instruction register in accordance with an output signal from the comparator and for outputting a control signal and a program count value change instruction; an execution unit for executing an instruction in accordance with a control signal from the instruction decoder; an edge detector for detecting an edge of an output signal from the reset controller and for outputting an edge detection signal; and an enable signal generator for outputting an enable signal in accordance with the edge detection signal and an output signal from the instruction decoder.
Claim 2
Dependent Claim
231 words
A central processing unit for preventing a program malfunction, comprising: a program counter for designating an address of an instruction to be executed; a first instruction register for storing an instruction outputted from a memory by the program counter; a second instruction register for fetching an instruction stored in the first instruction register in accordance with a first internal clock signal; a third instruction register for fetching an instruction stored in the first instruction register in accordance with a second internal clock signal; a comparator, which is operated in accordance with an enable signal, for comparing whether instructions stored in the second instruction register and the third instruction register are identical; a reset controller for outputting a reset signal in accordance with an output signal from the comparator; an instruction decoder for decoding an operation code of an instruction stored in the third instruction register in accordance with an output signal from the comparator and for outputting a control signal and a program count value change instruction; an execution unit for executing an instruction in accordance with a control signal from the instruction decoder; an edge detector for detecting an edge of an output signal from the reset controller and for outputting an edge detection signal; and an enable signal generator for outputting an enable signal in accordance with the edge detection signal and an output signal from the instruction decoder.
Claim 3
Dependent Claim
40 words
The CPU of claim 1, wherein said first internal clock signal is a falling edge detection signal of a first system clock for one cycle, and said second internal signal is a rising edge detection signal of each system clock.
Claim 4
Dependent Claim
28 words
The CPU of claim 1, wherein said enable signal generator outputs an enable signal of high level for a first period of a system clock at each cycle.
Claim 5
Dependent Claim
39 words
The CPU of claim 3, wherein said enable signal generator outputs a low level signal irrespective of the period of the system clock when the edge detection signal or the output signal from the instruction decoder is high level.
Claim 6
Dependent Claim
57 words
The CPU of claim 1, wherein said second instruction register is turned on at a falling edge of a first system clock for each cycle, said third instruction register is turned on at a rising edge for a second system clock, and is turned on at a rising edge at a start point of the next cycle.
Claim 7
Dependent Claim
32 words
The CPU of claim 1, wherein said reset controller shifts the level of the reset signal when the instructions stored in the second instruction register and the third instruction register are different.