Patent US5837591A successfully refreshed from Google Patents.
US5837591A
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Method of manufacturing a semiconductor device
Assignee: Panasonic Holdings Corp
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Filing: 1997-02-19
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Granted: 1998-11-17
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Expires: 2017-02-19
Abstract
Abstract A semiconductor device comprises silicon substrate 1 on which an integrated circuit is formed, first insulating layer 6 formed on silicon substrate 1, a capacitor comprising lower electrode 7 formed on first insulating layer 6, dielectric film 8 having a high dielectric constant and upper electrode 9, a second insulating film 11 having contact holes 13 which lead to lower electrode 7 and upper electrode 9 independently, diffusion barrier layer 17 which touches lower electrode 7 and upper electrode 9 at bottom of contact holes 13, and interconnection layer 15 formed on diffusion barrier layer 17. In diffusion barrier layer 17 at the bottom of contact hole 13, a lamellar region made of granular crystal is formed.
Inventors
- 👤 Yasuhiro Shimada
- 👤 Atsuo Inoue
- 👤 Koji Arita
- 👤 Toru Nasu
- 👤 Yoshihisa Nagano
- 👤 Akihiro Matsuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 13:04
CPC Classifications
H; H10; H10D; H10D84/00; H10B; H10B53/00; H10D1/00; H10D1/60; H10D1/68
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
158 words
A method of manufacturing a semiconductor device comprising the steps of: (a) forming a first insulating layer on a substrate on which an integrated circuit is formed, (b) forming a capacitor comprising a lower electrode, a dielectric film having a high dielectric constant, and an upper electrode on said first insulating layer, (c) forming a second insulating layer which covers said capacitor, (d) forming contact holes which lead to said lower electrode and upper electrode independently in said second insulating layer, (e) forming a diffusion barrier layer which covers at least the inside wall of said contact holes, and touches said lower electrode and said upper electrode at the bottom of said contact holes, wherein a layer thickness of said diffusion barrier layer is formed to be between 200 nm and 300 nm, (f) forming an interconnection layer on said diffusion barrier layer, and (g) providing heat treatment under a temperature ranging from 300° C. to 420° C.
Claim 2
Independent Claim
158 words
A method of manufacturing a semiconductor device comprising the steps of: (a) forming a first insulating layer on a substrate on which an integrated circuit is formed, (b) forming a capacitor comprising a lower electrode, a dielectric film having a high dielectric constant, and an upper electrode on said first insulating layer, (c) forming a second insulating layer which covers said capacitor, (d) forming contact holes which lead to said lower electrode and upper electrode independently in said second insulating layer, (e) forming a diffusion barrier layer which covers at least the inside wall of said contact holes, and touches said lower electrode and said upper electrode at the bottom of said contact holes, wherein a layer thickness of said diffusion barrier layer is formed to be between 200 nm and 300 nm, (f) forming an interconnection layer on said diffusion barrier layer, and (g) providing heat treatment under a temperature ranging from 300° C. to 420° C.
Claim 3
Dependent Claim
22 words
The method of manufacturing a semiconductor device of claim 1, wherein said heat treatment temperature ranges from 300° C. to 380° C.
Claim 4
Independent Claim
183 words
A method of manufacturing a semiconductor device comprising the steps of: (a) forming a first insulating layer on a substrate on which an integrated circuit is formed; (b) forming a capacitor comprising a lower electrode, a dielectric film having a high dielectric constant, and an upper electrode, on said first insulating layer; (c) forming a second insulating layer which covers said capacitor; (d) forming contact holes which lead to said lower electrode and said upper electrode independently in said second insulating layer; (e) forming a first diffusion barrier layer which covers at least an inside wall of said contact holes, and touches said lower electrode and said upper electrode at the bottom of said contact holes; (f) forming a second diffusion barrier layer on said first diffusion barrier layer, wherein said second diffusion barrier layer is same in material but different in crystal grain structure from said first diffusion barrier layer at a bottom of said contact holes; (g) forming an interconnection layer on said second diffusion barrier layer; and (h) providing heat treatment under a temperature ranging from 300° to 420° C.
Claim 5
Independent Claim
183 words
A method of manufacturing a semiconductor device comprising the steps of: (a) forming a first insulating layer on a substrate on which an integrated circuit is formed; (b) forming a capacitor comprising a lower electrode, a dielectric film having a high dielectric constant, and an upper electrode, on said first insulating layer; (c) forming a second insulating layer which covers said capacitor; (d) forming contact holes which lead to said lower electrode and said upper electrode independently in said second insulating layer; (e) forming a first diffusion barrier layer which covers at least an inside wall of said contact holes, and touches said lower electrode and said upper electrode at the bottom of said contact holes; (f) forming a second diffusion barrier layer on said first diffusion barrier layer, wherein said second diffusion barrier layer is same in material but different in crystal grain structure from said first diffusion barrier layer at a bottom of said contact holes; (g) forming an interconnection layer on said second diffusion barrier layer; and (h) providing heat treatment under a temperature ranging from 300° to 420° C.
Claim 6
Dependent Claim
21 words
The method of manufacturing a semiconductor device of claim 3, wherein said second diffusion barrier layer has a granular crystal structure.
Claim 7
Dependent Claim
30 words
The method of manufacturing a semiconductor device of claim 4, wherein a total thickness of said first and second diffusion barrier layers is formed between 200 nm and 300 nm.
Claim 8
Dependent Claim
33 words
The method of manufacturing a semiconductor device of claim 4, wherein said second diffusion barrier layer is formed of a thickness that is greater than a thickness of said first diffusion barrier layer.
References Cited (Backward Citations)
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| 3.5 Years (Year 4) | 2001-11-16 | 2002-05-18 | 2002-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-16 | 2006-05-18 | 2006-11-17 | $3760.00 | Window Closed / Lapsed |
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