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US5837571A Expired / Lapsed US ⏱️ 0.0 years remaining

High voltage transistor for sub-micron CMOS processes

Assignee: Texas Instruments Inc
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Filing: 1996-07-23
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Granted: 1998-11-17
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Expires: 2016-07-23
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Abstract

Abstract This invention relates to methodology to resolve the problem of low drain/source breakdown voltage (BVdss) in small geometry devices with thin gate oxide. Improved drain diffusion profile implanting through disjoint NSD/NWELL windows in the extended drain region, This provides essentially an improved lightly diffused (LDD) structure. Further this invention relates to alternative methods to resolve the problem of low drain/source breakdown voltage in other structures which can be achieved by for example, building a number of side wall oxide layers, impurity compensation or oxygen implantation. The improved LDD structure to which this invention relates has a number of advantages when compared with other solutions. It enables high voltage transistors to be fabricated with high drive capability, without additional process steps being required to implement the structure. The inventions will find applications wherever a high voltage capability is required to interface with the outside world. Such designs would include automotive applications; programming transistors for Field Programmable Gate Arrays; Robust I/O's and ESD Protection Circuits.

Inventors

  • 👤 Vijay Pathak

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 17:53
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/0221; H10D30/60; H10D30/601; H10D30/603; H10D62/00; H10D62/10; H10D62/102; H10D62/103; H10D62/105; H10D62/13; H10D62/149; H10D62/151; H10D64/00; H10D64/01; H10D64/021; H10P; H10P30/00; H10P30/20; H10P30/22; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/945

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 132 words
A method of forming a semiconductor device comprising the steps of: forming a layer of a first conductivity type on a substrate; forming source, drain and gate regions in said layer, one of said source and drain regions being formed by forming a mask over said layer having a plurality of disjoint windows of varying widths therein, said width variation being in conformance with a desired dopant profile; diffusing a dopant through said window to form said source or drain, said diffusion forming disjoint strips of dopant in said layer which vary in accordance with said width; heating said device to allow said dopant to diffuse into said layer to form a graded profile having a thickness which decreases towards said gate region; and forming a metal layer over said gate region.
Claim 2
Independent Claim 132 words
A method of forming a semiconductor device comprising the steps of: forming a layer of a first conductivity type on a substrate; forming source, drain and gate regions in said layer, one of said source and drain regions being formed by forming a mask over said layer having a plurality of disjoint windows of varying widths therein, said width variation being in conformance with a desired dopant profile; diffusing a dopant through said window to form said source or drain, said diffusion forming disjoint strips of dopant in said layer which vary in accordance with said width; heating said device to allow said dopant to diffuse into said layer to form a graded profile having a thickness which decreases towards said gate region; and forming a metal layer over said gate region.
Claim 3
Dependent Claim 26 words
The method of claim 1 wherein the step of forming said source or drain region comprises forming the region by NWELL/NSD diffusion through said mask window.
Claim 4
Dependent Claim 17 words
The method of claim 2 wherein said source and drain regions are formed in a single step.
Claim 5
Dependent Claim 28 words
The method of claim 1 wherein oxygen atoms are diffused to form said disjoint strips followed by a blanket implant diffusion to form said source or drain region.
Claim 6
Dependent Claim 24 words
The method of claim 1, wherein the step of forming the source and drain regions comprises forming the regions by an impurity compensation method.

References Cited (Backward Citations)

US3951694A Cited
US4371403A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-11-16 2002-05-18 2002-11-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-11-16 2006-05-18 2006-11-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-11-16 2010-05-18 2010-11-17 $7700.00 Window Closed / Lapsed

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