Patent EP0284176A2 successfully refreshed from Google Patents.
Patent US6162336A successfully refreshed from Google Patents.
Patent US1928241A successfully refreshed from Google Patents.
Patent US5837378A successfully refreshed from Google Patents.
US5837378A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of reducing stress-induced defects in silicon
Assignee: Micron Technology Inc
•
Filing: 1995-09-12
•
Granted: 1998-11-17
•
Expires: 2015-09-12
Abstract
Abstract A process for reducing stress during processing of semiconductor wafers comprising the steps of depositing a masking stack on a top and a bottom surface of the wafer and then removing at least a portion of the masking stack on the bottom surface prior to forming isolation regions on the top surface of the semiconductor wafer. In one embodiment, silicon nitride is formed on the top and the bottom surface of a silicon wafer. The silicon nitride is then patterned and etched on the top surface of the wafer to expose regions of the underlying silicon for field oxide formation. Prior to the field oxidation formation on the top side of the wafer, the silicon nitride layer on the bottom side of the wafer is removed so that a layer of silicon dioxide is formed on the bottom surface of the wafer during field oxidation formation. The layer of silicon dioxide on the bottom surface of the wafer reduces the stress in the regions of the silicon wafer adjacent the top surface of the wafer and thereby reduces the formation of stress induced defects in this region of the silicon wafer. The layer of silicon dioxide on the bottom surface of the wafer can then be removed.
Inventors
- 👤 Viju K. Mathews
- 👤 Nanseng Jeng
- 👤 Pierre C. Fazan
- 👤 Thomas A. Figura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:18
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/10; H10W10/13
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
127 words
A process for reducing stress in semiconductor wafers during semiconductor processing, comprising the steps of: forming a masking stack on a top side and a bottom side of the semiconductor wafer, the masking stack forming step comprising depositing a layer of pad oxide and a layer of silicon nitride on a top side and a bottom side of the semiconductor wafer; removing substantially all of said masking stack on said bottom side of said semiconducting wafer, said removing step comprising removing said silicon nitride layer and said pad oxide layer from said bottom side of said semiconductor wafer; and forming subsequent to said removing step, isolation regions at selected locations on said top side of said semiconductor wafer that will isolate active areas of said semiconductor wafer.
Claim 2
Dependent Claim
127 words
A process for reducing stress in semiconductor wafers during semiconductor processing, comprising the steps of: forming a masking stack on a top side and a bottom side of the semiconductor wafer, the masking stack forming step comprising depositing a layer of pad oxide and a layer of silicon nitride on a top side and a bottom side of the semiconductor wafer; removing substantially all of said masking stack on said bottom side of said semiconducting wafer, said removing step comprising removing said silicon nitride layer and said pad oxide layer from said bottom side of said semiconductor wafer; and forming subsequent to said removing step, isolation regions at selected locations on said top side of said semiconductor wafer that will isolate active areas of said semiconductor wafer.
Claim 3
Dependent Claim
107 words
The method of claim 1, wherein said step of forming isolation regions at selected locations on said top side of said semiconductor wafer comprises the steps of: depositing a layer of photoresist material to expose one or more regions of said layer of silicon nitride on said top surface of said silicon wafer; etching said one or more exposed regions of silicon nitride to expose one or more regions of said pad oxide; etching said one or more exposed regions of pad oxide to expose one or more regions of said silicon wafer; and forming field oxide isolation regions in said exposed regions of said silicon wafer.
Claim 4
Dependent Claim
45 words
The process of claim 2, wherein said step of forming field oxide regions in said exposed regions of said silicon wafer comprises exposing said silicon wafer to an oxygen carrying gas in an oven so that said exposed regions of said silicon wafer are oxidized.
Claim 5
Dependent Claim
39 words
The process of claim 3, wherein said step of forming said field oxide regions in said exposed regions of said silicon wafer results in a layer of silicon dioxide being formed on the bottom surface of said silicon wafer.
Claim 6
Dependent Claim
24 words
The process of claim 4, further comprising the step of removing the layer of silicon dioxide on said bottom surface of said silicon wafer.
Claim 7
Dependent Claim
175 words
A process for producing a silicon wafer having reduced stress in regions adjacent an upper surface of said wafer, comprising the steps of forming a layer of pad oxide on the top and bottom surfaces of said silicon wafer; depositing a layer of silicon nitride on said layer of pad oxide on the top and bottom surfaces of said silicon wafer; etching said layers of silicon nitride and pad oxide from siad bottom surface of said wafer; subsequent to etching said layers of silicon nitride and pad oxide from said bottom surface, forming field oxidation isolation regions on said top surface of said silicon wafer, wherein said step of forming field oxidation isolation regions results in the formation of a layer of silicon dioxide on said bottom surface of said silicon wafer and wherein said layer of silicon dioxide reduces stresses in regions of said silicon wafer adjacent said top surface resulting from said formation of field oxidation isolation regions; and removing said layer of silicon dioxide on said bottom surface of said silicon wafer.
Claim 8
Dependent Claim
175 words
A process for producing a silicon wafer having reduced stress in regions adjacent an upper surface of said wafer, comprising the steps of forming a layer of pad oxide on the top and bottom surfaces of said silicon wafer; depositing a layer of silicon nitride on said layer of pad oxide on the top and bottom surfaces of said silicon wafer; etching said layers of silicon nitride and pad oxide from siad bottom surface of said wafer; subsequent to etching said layers of silicon nitride and pad oxide from said bottom surface, forming field oxidation isolation regions on said top surface of said silicon wafer, wherein said step of forming field oxidation isolation regions results in the formation of a layer of silicon dioxide on said bottom surface of said silicon wafer and wherein said layer of silicon dioxide reduces stresses in regions of said silicon wafer adjacent said top surface resulting from said formation of field oxidation isolation regions; and removing said layer of silicon dioxide on said bottom surface of said silicon wafer.
Claim 9
Dependent Claim
21 words
The process of claim 6, further comprising depositing a polysilicon layer between the pad oxide layer and the silicon nitride layer.
Claim 10
Dependent Claim
24 words
The process of claim 6, further comprising depositing a polysilicon layer over the silicon nitride layer prior to the step of patterning and etching.
Claim 11
Dependent Claim
23 words
The process of claim 6 further comprising depositing a polysilicon layer over the silicon wafer subsequent to the step of patterning and etching.
Claim 12
Dependent Claim
112 words
The method of claim 6, wherein the step of forming field oxidation isolation regions comprises: positioning a layer of photoresist material on said layer of silicon nitride on said top surface of said silicon wafer; patterning and etching said layer of photoresist material to expose one or more regions of said silicon nitride; etching said silicon nitride in said one or more exposed regions to expose one or more regions of said pad oxide; etching said pad oxide in said one or more exposed regions to expose one or more regions of said silicon wafer; and growing field oxidation isolation regions in said one or more exposed regions of said silicon wafer.
Claim 13
Dependent Claim
36 words
The process of claim 10, wherein said step of growing field oxidation isolation regions results in active regions of said silicon wafer adjacent said top surface of said silicon wafer being electrically isolated from one another.
Claim 14
Dependent Claim
21 words
The process of claim 11, further comprising the step of forming active devices in said active regions of said silicon wafers.
Claim 15
Dependent Claim
42 words
The process of claim 12, wherein said active devices in said active regions of said silicon wafer have a reduced leakage current as a result of said step of removing said silicon nitride layer from said bottom surface of said silicon wafer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-16 | 2002-05-18 | 2002-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-16 | 2006-05-18 | 2006-11-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-16 | 2010-05-18 | 2010-11-17 | $7700.00 | Window Closed / Lapsed |