Abstract Methods and apparatus for controlling output buffer circuitry in a synchronous semiconductor memory device. An internal clock signal is generated and logic provided to provide a control signal that enables that output buffer circuitry for a read operation. An internal clock signal is generated synchronized to the external or system clock signal. An intermediate control signal is triggered by the internal clock signal at a selected number of cycles less than the memory latency period after a read command, and then the control signal for enabling the output buffer is asserted on a subsequent cycle of the internal clock signal, thereby ensuring at least a predetermined minimum time for the output buffer control signal to propagate through the memory device before data is transferred out of the device.
A method for controlling a data output buffer of a synchronous semiconductor memory device for high speed operation wherein the memory has a read latency period of a predetermined number of clock cycles, the method comprising the steps of: receiving a periodic system clock signal having at least a predetermined period; generating an internal clock signal synchronized to the system clock signal; asserting an intermediate control signal upon a rising edge of the internal clock signal at a time equal to a selected number of clock cycles less than the said latency period after a read command; and then generating a control signal for enabling the output buffer upon the rising edge of a next subsequent cycle of the internal clock signal, thereby ensuring at least a predetermined minimum time for the output buffer enabling control signal to propagate through the memory before data is transferred out of the memory device.
Claim 2
Independent Claim
151 words
A method for controlling a data output buffer of a synchronous semiconductor memory device for high speed operation wherein the memory has a read latency period of a predetermined number of clock cycles, the method comprising the steps of: receiving a periodic system clock signal having at least a predetermined period; generating an internal clock signal synchronized to the system clock signal; asserting an intermediate control signal upon a rising edge of the internal clock signal at a time equal to a selected number of clock cycles less than the said latency period after a read command; and then generating a control signal for enabling the output buffer upon the rising edge of a next subsequent cycle of the internal clock signal, thereby ensuring at least a predetermined minimum time for the output buffer enabling control signal to propagate through the memory before data is transferred out of the memory device.
Claim 3
Dependent Claim
17 words
A method according to claim 1 wherein the selected number of clock cycles is one clock cycle.