Patent US5832310A successfully refreshed from Google Patents.
US5832310A
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Serial I/O channel having dependent and synchronous sources of control data and user defined data
Assignee: Unisys Corp
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Filing: 1997-02-04
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Granted: 1998-11-03
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Expires: 2017-02-04
Abstract
Abstract Apparatus is provided for transferring user defined data from a parallel storage medium to a serial link driver in an I/O channel subsystem of a processor or I/O device controller. The serial link driver transmits a frame of user defined data over a serial data transfer medium. A data buffer receives and stores user defined data from the parallel storage medium. A control data facility that is distinct from the data buffer forms and transmits control data from the sender of the frame to the recipient of the frame via a path that does not include the data buffer. The control data facility includes respectively different dedicated logic for asynchronously generating each of the following: special character sequences, frame delimiters, headers, and cyclic redundancy checksums. A switching facility receives the user defined data from the data buffer. The switching facility also receives control data from the control data facility. The switching facility provides either the user defined data or the control data to the serial link driver. A data path control mechanism signals the switching facility to alternately provide the control data and the user defined data to the serial link driver, thereby forming frames.
Inventors
- 👤 Douglas E. Morrissey
- 👤 Edward T. Cavanagh, Jr.
- 👤 Gene T. Wieder
- 👤 Kin H. Ng
- 👤 William E. Oldham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 12:14
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/122
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
211 words
An input/output (I/O) channel subsystem for a host computing system which includes an interface for generating a frame of serial data from the host computer source of parallel user data, said channel subsystem comprising: a source of parallel user data, a data buffer for receiving parallel user data from said source of parallel user data, an interface coupled to said data buffer for receiving user data from and for supplying user data to said data buffer, said interface comprising frame generator means including a frame protocol generator for generating frame protocol signals which define elements of a frame, said interface including a logic switch having a plurality of logic gating means connected in series for assimilating user data signals together with said frame protocol signals, a source of parallel bit user data signals being coupled to said data buffer and having an output connected to the input of a first one of said plurality of said gating means, said frame protocol generating means being connected to another of said inputs of said first one of said gating means, and data path control means coupled to said plurality of logic gating means for control of said assimilation of a frame of data comprising said user data signals interleaved between said protocol signals.
Claim 2
Dependent Claim
211 words
An input/output (I/O) channel subsystem for a host computing system which includes an interface for generating a frame of serial data from the host computer source of parallel user data, said channel subsystem comprising: a source of parallel user data, a data buffer for receiving parallel user data from said source of parallel user data, an interface coupled to said data buffer for receiving user data from and for supplying user data to said data buffer, said interface comprising frame generator means including a frame protocol generator for generating frame protocol signals which define elements of a frame, said interface including a logic switch having a plurality of logic gating means connected in series for assimilating user data signals together with said frame protocol signals, a source of parallel bit user data signals being coupled to said data buffer and having an output connected to the input of a first one of said plurality of said gating means, said frame protocol generating means being connected to another of said inputs of said first one of said gating means, and data path control means coupled to said plurality of logic gating means for control of said assimilation of a frame of data comprising said user data signals interleaved between said protocol signals.
Claim 3
Dependent Claim
73 words
Apparatus of claim 1, wherein said source of user data signals includes an unpacking means coupled to said data buffer to receive parallel user data and convert said parallel user data to serial format, said unpacking means comprising: an unpacker control means, a plurality of memory registers to temporarily store portions of said parallel user data signals, and a logic multiplexer to transmit the contents of one of said plurality of memory registers.
Claim 4
Dependent Claim
151 words
Apparatus of claim 1, wherein said source of user data signals further includes a first in, first out (FIFO) circuit: said FIFO circuit comprising: an FIFO control means, a header checker/generator to check block header information received along with user data from data buffer to be transmitted by said channel subsystem, and to generate said block header information when frame data has been received by said channel subsystem, an error detection code (EDC) generator/checker to check block EDC information received along with user data from data buffer to be transmitted by said channel subsystem, and to generate said block EDC information when frame data has been received by said channel subsystem, a temporary buffer to hold user data signals that do not contain said additional control signals, and means for forming and transmitting a signal to said data path control when temporary buffer contains enough user data to transmit a frame.
Claim 5
Dependent Claim
16 words
Apparatus as set forth in claim 3 wherein said subsystem further includes a serial channel microprocessor.
Claim 6
Dependent Claim
58 words
Apparatus of claim 4, wherein said header checker/generator and said EDC generator/checker are used when receiving data on the said channel subsystem to generate block header and EDC information to be included along with received user data when said user data is stored in data buffer, both occurring using hardware logic with minimal dependence on said channel microprocessor.
Claim 7
Dependent Claim
87 words
Apparatus of claim 1, wherein said apparatus receives a request for data from a recipient, the apparatus further comprising: means for counting and storing a count of how many requests for data have been received asynchronously from said channel microprocessor, means for modifying, using hardware without microprocessor intervention, the control data in a single frame to indicate to the recipient that the request has been received, and means for decrementing the count in said counting means when the single frame containing modified control data has been transmitted.
Claim 8
Dependent Claim
58 words
Apparatus as set forth in claim 1, wherein said frame generator means further includes cycle burst control means for indicating to said data path control means: a) size of the frame to be formed and the amount of user defined data to be included in the frame, and b) whether formation of a subsequent frame should be started.
Claim 9
Dependent Claim
80 words
Apparatus of claim 1, wherein access to said data buffer is controlled by direct memory access (DMA) logic, and said DMA logic includes: means for allocating a plurality of buffer areas within the parallel storage medium, means for determining an amount of user defined data available for transmission within a respective one of the buffer areas, and means for transmitting a grant signal to the unpacking control means to indicate that a predetermined amount of data is available for transmission.
Claim 10
Dependent Claim
58 words
Apparatus as set forth in claim 1, wherein data path control means further includes means for generating additional control data characters, said generating means comprising of: a plurality of sequence generators, each sequence generator transmitting a respective predetermined bit sequence that defines a respective special character, and selection logic to select one of said bit sequences for transmission.
Claim 11
Dependent Claim
91 words
Apparatus as set forth in claim 1, wherein said fiber optic interface further includes frame receiving means: said frame receiving means including: sequence receive logic to provide signals to channel microprocessor regarding changes to channel link status, frame recognition logic to detect frame protocol signals which define a frame, frame protocol verification means for verifying received frame protocol signals, frame counter to count the number of bytes in the received frame, violation/realign logic to handle alignment errors in data reception, and switch control logic to direct flow of received frame signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-02 | 2002-05-04 | 2002-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-02 | 2006-05-04 | 2006-11-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-02 | 2010-05-04 | 2010-11-03 | $7700.00 | Window Closed / Lapsed |