US4866609A
Expired / Lapsed
US
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Byte count handling in serial channel extender with buffering for data pre-fetch
Assignee: International Business Machines Corp
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Filing: 1988-09-21
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Granted: 1989-09-12
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Expires: 2008-09-21
Abstract
Abstract A channel subsystem with a conventional serial extender link that causes communications between a channel and a control unit to be delayed by the additional time to transmit a message in one direction and to transmit an acknowledgement in the other direction. The channel subsystem also has a buffer and associated components (called a channel outboard box) that are used for prefetching data from processor memory or from a peripheral device without waiting for the acknowledgment routines that are commonly used on both an interlocked data transfer and a non-interlocked transfer (called data streaming). A system of counters and other components and associated operations maintain the correct byte count that would otherwise be maintained in a system without the prefetch buffer and with only a short serial link. A system of count and status frames provides for sending byte count and other status information between the channel and the outboard box.
Inventors
- 👤 Salvatore A. Calta
- 👤 Thomas A. Gregg
- 👤 Leon Skarshinski
- 👤 Richard Strangwayes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 21:58
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/122
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
316 words
A data processing system having apparatus (22) for interconnecting a parallel bus (26, 27) of a control unit (18) and a serial link (14) of a channel, said apparatus comprising: means (47) for storing a byte count, a buffer memory (39), a parallel bus (27m) for data to be stored in the buffer memory and a parallel bus (36) for data fetched from the buffer memory, means (30b) connected between said parallel busses of said buffer and connected to said parallel bus of the control unit for handling data transfer operations on said parallel bus according to a predetermined protocol, means (28, 29) connected to said serial link for sending and receiving frames on the serial link, said sending and receiving means including means for converting between a serial format of incoming or outgoing frames on the serial link and a parallel format of the control unit parallel bus and the buffer memory, means interconnecting said buffer memory, said means for handling operations on said parallel bus, and said sending and receiving means and controlling data transfers between said means connected to said serial link and said means for handling operations on said parallel bus, the frame format including a data field and a command field, the command field holding a selected one of a plurality of binary codes signifying the contents of the data field, a first command code signifying a data field containing a byte count for a data transfer and a second command code signifying a data field containing data for controlling the subsequent transfer of data to or from the control unit in an interlocked mode or a non-interlocked mode, and means (37) in said interconnecting and controlling means for decoding the command field of an incoming frame on said serial link and means (41) for transferring a byte count data field in an incoming frame to said byte count storing means.
Claim 2
Dependent Claim
316 words
A data processing system having apparatus (22) for interconnecting a parallel bus (26, 27) of a control unit (18) and a serial link (14) of a channel, said apparatus comprising: means (47) for storing a byte count, a buffer memory (39), a parallel bus (27m) for data to be stored in the buffer memory and a parallel bus (36) for data fetched from the buffer memory, means (30b) connected between said parallel busses of said buffer and connected to said parallel bus of the control unit for handling data transfer operations on said parallel bus according to a predetermined protocol, means (28, 29) connected to said serial link for sending and receiving frames on the serial link, said sending and receiving means including means for converting between a serial format of incoming or outgoing frames on the serial link and a parallel format of the control unit parallel bus and the buffer memory, means interconnecting said buffer memory, said means for handling operations on said parallel bus, and said sending and receiving means and controlling data transfers between said means connected to said serial link and said means for handling operations on said parallel bus, the frame format including a data field and a command field, the command field holding a selected one of a plurality of binary codes signifying the contents of the data field, a first command code signifying a data field containing a byte count for a data transfer and a second command code signifying a data field containing data for controlling the subsequent transfer of data to or from the control unit in an interlocked mode or a non-interlocked mode, and means (37) in said interconnecting and controlling means for decoding the command field of an incoming frame on said serial link and means (41) for transferring a byte count data field in an incoming frame to said byte count storing means.
Claim 3
Dependent Claim
70 words
The apparatus of claim 1 including means in said decoding means for decoding a frame signifying whether data in forthcoming data transfer operation is to be stored temporarily in said buffer memory or to bypass said buffer memory and means in said interconnecting means for transmitting data between said control unit and said channel through said buffer memory or bypassing said buffer memory according to information in said signifying frame.
Claim 4
Dependent Claim
56 words
The apparatus of claim 2 wherein said signifying frame contains a third command code signifying that the data field contains information for the apparatus, and said means for transmitting data between said control unit and said channel includes means responsive to information in said data field for transmitting data through said buffer or bypassing said buffer.
Claim 5
Dependent Claim
144 words
The data processing system of claim 1 wherein said channel includes a frame counter and a buffer and means for updating said frame counter as bytes are transferred and as bytes are acknowledged, whereby on an input operation a predetermined frame counter value signifies that the channel buffer is full and on an output operation a predetermined frame counter value signifies that said buffer memory of said apparatus is full or almost full, means for setting the frame counter to a predetermined value at the beginning of an input or output operation and means for producing an error signal if the frame counter does not contain said predetermined value at the end of the operation, and means for limiting the transfer of data from the channel in response to the value in the frame counter to avoid overrrunning said buffer memory of said apparatus.
Claim 6
Dependent Claim
49 words
The data processing system of claim 4 wherein said channel includes a separate channel front end and wherein said channel front end includes means for communicating with the channel on a parallel bus and means for communicating with said apparatus on the serial link and includes said frame counter.
Claim 7
Dependent Claim
74 words
The apparatus of claim 1 wherein said interconnecting means includes means for updating said means for storing a byte count when a byte is transferred from said buffer to said parallel bus of said control unit and means for forming a serial frame containing a third command code signifying that the data field of the frame contains a byte count and means for sending the byte count to the channel during a write operation.
Claim 8
Dependent Claim
27 words
The apparatus of claim 6 wherein said interconnecting means includes means for calculating the residual count and sending it to the channel in a residual count frame.
Claim 9
Dependent Claim
40 words
The apparatus of claim 6 wherein said interconnecting means includes means for forming a frame for signaling to the channel that the apparatus has sent to the control unit a signal (Command Out) to end a read or write operation.
Claim 10
Dependent Claim
46 words
The apparatus of claim 6 wherein said interconnecting means includes means in said apparatus for forming a frame for signaling to the channel that more bytes were received and acknowledged by the control unit than required by the count sent to the apparatus by the channel.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-11 | 1993-03-13 | 1993-09-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-11 | 1997-03-13 | 1997-09-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-11 | 2001-03-13 | 2001-09-12 | $7700.00 | Window Closed / Lapsed |