Method and system for adjusting a clock signal within electronic circuitry

Claim 1

An integrated circuit clock adjusting apparatus, comprising: a source of master clock signals; a first clock signal generator circuit, connected to receive master clock signals at an input node and to generate a first clock signal with a first delay at an output node, the first delay defined by a regenerator circuit metallization creating one of at least three possible different metallization selectable incremental delays available within the first clock signal regenerator circuit; a first latch responsive to the first clock signal for latching logic signals outputted from a first logic circuit; a second clock signal regenerator circuit, connected to receive master clock signals at an input node and to generate a second clock signal with a second delay at an output node, the second delay defined by a regenerator circuit metallization creating one of at least three possible different metallization selectable incremental delays available within the second clock signal generator circuit, the second delay of the second clock signal regenerator circuit differing from the first delay of the first clock signal regenerator circuit; and a second latch responsive to the second clock signal for latching logic signals received from said first latch via a second logic circuit.