Patent US5828854A successfully refreshed from Google Patents.
US5828854A
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Method and apparatus for multiplexing signals from a bus bridge to an ISA bus interface and an ATA bus interface
Assignee: Intel Corp
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Filing: 1996-09-26
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Granted: 1998-10-27
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Expires: 2016-09-26
Abstract
Abstract An apparatus and method for connecting a bus bridge to a plurality of bus interfaces are disclosed. The invention allows output lines on a bus bridge to be shared so that a minimal amount of dedicated pins are utilized. Signals on the bus bridge which need to be driven and received quickly are connected directly from the bus bridge to the bus interfaces. Signals on the bus bridge which do not need to be driven and received quickly are connected from the bus bridge to the bus interfaces though buffers. The invention allows the bus bridge to interface a high speed local bus and a plurality of I/O buses while satisfying the timing requirements of each of the I/O buses.
Inventors
- 👤 Nicholas D. Wade
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:29
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/405
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
74 words
An apparatus, comprising: a first plurality of pins that transmit first bus signals with tight timing requirements to a first bus and that transmit second bus signals with timing requirements that are not tight to a second bus; and a second plurality of pins that transmit second bus signals with tight timing requirements to the second bus and that transmit first bus signals with timing requirements that are not tight to the first bus.
Claim 2
Independent Claim
74 words
An apparatus, comprising: a first plurality of pins that transmit first bus signals with tight timing requirements to a first bus and that transmit second bus signals with timing requirements that are not tight to a second bus; and a second plurality of pins that transmit second bus signals with tight timing requirements to the second bus and that transmit first bus signals with timing requirements that are not tight to the first bus.
Claim 3
Dependent Claim
21 words
The apparatus of claim 1, wherein the first bus is an ISA bus and the second bus is an ATA bus.
Claim 4
Dependent Claim
18 words
The apparatus of claim 1, wherein the first bus signals with tight timing requirements are latched address signals.
Claim 5
Dependent Claim
18 words
The apparatus of claim 1, wherein the second bus signals with tight timing requirements are disk data signals.
Claim 6
Dependent Claim
21 words
The apparatus of claim 1, wherein the second bus signals with timing requirements that are not tight are disk address signals.
Claim 7
Dependent Claim
21 words
The apparatus of claim 1, wherein the second bus signals with timing requirements that are not tight are chip select signals.
Claim 8
Dependent Claim
21 words
The apparatus of claim 1, wherein the first bus signals with timing requirements that are not tight are system address signals.
Claim 9
Dependent Claim
23 words
The apparatus of claim 1, wherein the first bus signals with timing requirements that are not tight are system byte high enable signals.
Claim 10
Independent Claim
40 words
An apparatus, comprising: direct connections, from the apparatus to a first bus and a second bus, that transmit signals with tight timing requirements; and buffered connections, from the direct connections, that transmit signals with timing requirements that are not tight.
Claim 11
Independent Claim
40 words
An apparatus, comprising: direct connections, from the apparatus to a first bus and a second bus, that transmit signals with tight timing requirements; and buffered connections, from the direct connections, that transmit signals with timing requirements that are not tight.
Claim 12
Dependent Claim
21 words
The apparatus of claim 9, wherein the first bus is an ISA bus and the second bus is an ATA bus.
Claim 13
Dependent Claim
20 words
The apparatus of claim 9, wherein the signals with tight timing requirements are latched address signals and disk data signals.
Claim 14
Dependent Claim
19 words
The apparatus of claim 9, wherein the signals with timing requirements that are not tight are disk address signals.
Claim 15
Dependent Claim
19 words
The apparatus of claim 9, wherein the signals with timing requirements that are not tight are chip select signals.
Claim 16
Dependent Claim
19 words
The apparatus of claim 9, wherein the signals with timing requirements that are not tight are system address signals.
Claim 17
Dependent Claim
20 words
The apparatus of claim 9, wherein the signals with timing requirements that are not tight are byte high enable signals.
Claim 18
Dependent Claim
74 words
A bus bridge transmitting signals to an ISA bus and an ATA bus, comprising: a first direct connection, from the bus bridge to the ISA bus, that transmits latched address signals; a second direct connection, from the bus bridge to the ATA bus, that transmits disk data signals, disk address signals, and chip select signals; a first buffered connection, from the second direct connection, that transmits system address and system byte high enable signals.
Claim 19
Dependent Claim
74 words
A bus bridge transmitting signals to an ISA bus and an ATA bus, comprising: a first direct connection, from the bus bridge to the ISA bus, that transmits latched address signals; a second direct connection, from the bus bridge to the ATA bus, that transmits disk data signals, disk address signals, and chip select signals; a first buffered connection, from the second direct connection, that transmits system address and system byte high enable signals.
Claim 20
Dependent Claim
79 words
A bus bridge transmitting signals to an ISA bus and an ATA bus, comprising: a first direct connection, from the bus bridge to the ISA bus, that transmit latched address signals, system address signals, and system byte high enable signals; a second direct connection, from the bus bridge to the ATA bus, that transmits disk data signals; and a first buffered connection, from the first direct connection to the ATA interface, that transmits disk address and chip select signals.
Claim 21
Dependent Claim
79 words
A bus bridge transmitting signals to an ISA bus and an ATA bus, comprising: a first direct connection, from the bus bridge to the ISA bus, that transmit latched address signals, system address signals, and system byte high enable signals; a second direct connection, from the bus bridge to the ATA bus, that transmits disk data signals; and a first buffered connection, from the first direct connection to the ATA interface, that transmits disk address and chip select signals.
Claim 22
Independent Claim
51 words
A method for transmitting signals to a first bus and a second bus, comprising: transmitting signals with tight timing requirements on direct connections from a bus bridge to the first bus and the second bus; transmitting signals with timing requirements that are not tight on buffered connections from the direct connections.
Claim 23
Independent Claim
51 words
A method for transmitting signals to a first bus and a second bus, comprising: transmitting signals with tight timing requirements on direct connections from a bus bridge to the first bus and the second bus; transmitting signals with timing requirements that are not tight on buffered connections from the direct connections.
Claim 24
Dependent Claim
21 words
The method of claim 18, wherein the first bus is an ISA bus and the second bus is an ATA bus.
Claim 25
Dependent Claim
20 words
The method of claim 18, wherein the signals with tight timing requirements are latched address signals and disk data signals.
Claim 26
Dependent Claim
19 words
The method of claim 18, wherein the signals with timing requirements that are not tight are disk address signals.
Claim 27
Dependent Claim
19 words
The method of claim 18, wherein the signals with timing requirements that are not tight are chip select signals.
Claim 28
Dependent Claim
19 words
The method of claim 18, wherein the signals with timing requirements that are not tight are system address signals.
Claim 29
Dependent Claim
21 words
The method of claim 18, wherein the signals with timing requirements that are not tight are system byte high enable signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-26 | 2002-04-27 | 2002-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-26 | 2006-04-27 | 2006-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-26 | 2010-04-27 | 2010-10-27 | $7700.00 | Window Closed / Lapsed |