Patent US5828592A successfully refreshed from Google Patents.
US5828592A
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US
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Analog signal recording and playback integrated circuit and message management system
Assignee: Winbond Electronics Corp
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Filing: 1997-03-12
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Granted: 1998-10-27
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Expires: 2017-03-12
Abstract
Abstract An apparatus and method for message management using nonvolatile analog signal recording and playback is disclosed. The device is an integrated circuit with interface circuitry for use as a peripheral device to a microcontroller or a microprocessor-based system. The integrated circuit is complete with differential analog inputs, auto attenuation to improve signal quality, filter, fixed references including a band gap reference, trimming, memory array, multiple closed loop sample and hold circuits, column device, row decoder, address counters, master oscillator, chip function timing circuits, and a serial peripheral interface (SPI) and circuits on a single chip. The integrated circuit is interfaced with a host microcontroller through the SPI. The host microcontroller can send a number of commands to the integrated circuit through the SPI for efficient message management. These commands include the basic commands to record or playback and various addressing and message cueing options. The system utilizes redundancy to increase production yield. It also utilizes a high speed test mode to reduce production testing time.
Inventors
- 👤 Hieu Van Tran
- 👤 Nataraj S. Bindiganavale
- 👤 Anthony Dunne
- 👤 Boyce W. Jarrett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 20:39
CPC Classifications
G; G06; G06F; G06F3/00; G11; G11C; G11C27/00; G11C27/005; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/44
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
91 words
A nonvolatile integrated circuit analog storage device having the capability of receiving, repetitively sampling, storing and reproducing an analog input signal comprising: a first circuit for sampling an analog signal; a plurality of analog storage cells coupled to the first circuit, for storing samples of the analog signal; and a second circuit for reading out the stored samples of the analog signal to reconstruct the analog signal, the second circuit including an attenuator for attenuating noise in the reconstructed analog signal when the reconstructed analog signal is below a predetermined threshold.
Claim 2
Dependent Claim
91 words
A nonvolatile integrated circuit analog storage device having the capability of receiving, repetitively sampling, storing and reproducing an analog input signal comprising: a first circuit for sampling an analog signal; a plurality of analog storage cells coupled to the first circuit, for storing samples of the analog signal; and a second circuit for reading out the stored samples of the analog signal to reconstruct the analog signal, the second circuit including an attenuator for attenuating noise in the reconstructed analog signal when the reconstructed analog signal is below a predetermined threshold.
Claim 3
Dependent Claim
50 words
The device of claim 1, further comprising: an interface circuit coupled to the first circuit, the second circuit and the plurality of analog storage cells; and a microcontroller coupled to the interface circuit for controlling the sampling and storage of the analog signal and the reading of the stored samples.
Claim 4
Dependent Claim
26 words
The device of claim 2, wherein the microcontroller provides a clock signal for synchronizing data transfer into the first circuit and out of the second circuit.
Claim 5
Dependent Claim
112 words
The device of claim 2, wherein the interface circuit comprises: an input shift register for receiving control and address information from the microcontroller; a logic circuit coupled to the input shift register for receiving the control information, the logic circuit generating an output signal in response to the control information; an address circuit coupled to the input shift register and to the logic circuit receiving the address information from the input shift register in response to the output signal; and an output shift register coupled to the logic circuit and to the address circuit, the address circuit providing the address information to the output shift register in response to the output signal.
Claim 6
Dependent Claim
25 words
The device of claim 4, wherein the control information and address information include information for initiating reading of the stored samples at a specified address.
Claim 7
Dependent Claim
26 words
The device of claim 4, wherein the control information and address information include information for initiating reading of the stored samples at a next available address.
Claim 8
Dependent Claim
73 words
The nonvolatile integrated circuit analog storage device of claim 1, wherein the second circuit further comprises a peak detector coupled to the attenuator that determines if the read samples of the analog signal are below a predetermined threshold, the peak detector generating a signal if the read samples of the analog signal are below a predetermined threshold, wherein the attenuator attenuates the read samples of the analog signal in response to the signal.
Claim 9
Dependent Claim
43 words
The nonvolatile integrated circuit analog storage device of claim 1, wherein in a high speed read mode, the second circuit reads the stored samples, compares each stored sample with a reference voltage, and shifts out the result of the comparisons at high speed.
Claim 10
Dependent Claim
107 words
The nonvolatile integrated circuit analog storage device of claim 1, wherein the input signal includes a first portion and a second portion, the device further comprising a fixed gain amplifier that has a first input terminal, a second input terminal and an output terminal, the first input terminal being coupled to receive the first portion of the input signal via a first resistor, the output terminal being coupled to the first input terminal via a second resistor, the second input terminal being coupled to receive the second portion via a third resistor, the second input terminal also being coupled to a ground terminal via a fourth signal.
Claim 11
Dependent Claim
19 words
The nonvolatile integrated circuit analog storage device of claim 9, wherein the input signal is a differential input signal.
Claim 12
Independent Claim
68 words
A method of recording and playback of messages of varying length, comprising the steps of: (a) sampling an analog signal; (b) storing samples of the analog signal in a plurality of analog storage cells; (c) reading out the stored samples of the analog signal to reconstruct the analog signal; and (d) attenuating noise in the reconstructed analog signal when the reconstructed analog signal is below a predetermined threshold.
Claim 13
Independent Claim
68 words
A method of recording and playback of messages of varying length, comprising the steps of: (a) sampling an analog signal; (b) storing samples of the analog signal in a plurality of analog storage cells; (c) reading out the stored samples of the analog signal to reconstruct the analog signal; and (d) attenuating noise in the reconstructed analog signal when the reconstructed analog signal is below a predetermined threshold.
Claim 14
Dependent Claim
29 words
The method of claim 11, further comprising the step of providing a microcontroller for controlling the sampling of the analog signal and the reading out of the stored samples.
Claim 15
Dependent Claim
26 words
The method of claim 12, wherein the microcontroller provides a clock signal for synchronizing sampling of the analog signal and reading out of the stored samples.
Claim 16
Dependent Claim
116 words
The method of claim 12, further comprising the steps of: providing an input shift register for receiving control and address information from the microcontroller; providing a logic circuit coupled to the input shift register for receiving the control information, the logic circuit generating an output signal in response to the control information; providing an address circuit coupled to the input shift register and to the logic circuit receiving the address information from the input shift register in response to the output signal; and providing an output shift register coupled to the logic circuit and to the address circuit, the address circuit providing the address information to the output shift register in response to the output signal.
Claim 17
Dependent Claim
25 words
The method of claim 14, wherein the control information and address information include information for initiating reading of the stored samples at a specified address.
Claim 18
Dependent Claim
26 words
The method of claim 14, wherein the control information and address information include information for initiating reading of the stored samples at a next available address.
Claim 19
Dependent Claim
60 words
The method of claim 11, wherein step (d) further comprises the steps of: (d.1) determining if the read samples of the analog signal are below a predetermined threshold; (d.2) generating a signal if the read samples of the analog signal are below a predetermined threshold; and (d.3) attenuating the read samples of the analog signal in response to the signal.
Claim 20
Dependent Claim
49 words
The method of claim 11, wherein step (c) comprises the steps of: (c.1) reading the stored samples during a high speed read mode; (c.2) comparing each stored sample with a reference voltage; and (c.3) shifting out the result of the comparisons at high speed to reconstruct the analog signal.
Claim 21
Dependent Claim
18 words
The method of claim 11, further comprising the step of amplifying the analog signal prior to step (a).
Claim 22
Dependent Claim
146 words
A nonvolatile integrated circuit analog storage device having the capability of receiving, repetitively sampling, storing and reproducing an analog input signal comprising: a first circuit that samples an analog signal; a plurality of analog storage cells coupled to the first circuit, that stores samples of the analog signal; a second circuit that reads out the stored samples of the analog signal to reconstruct the analog signal; an interface circuit coupled to the first circuit, the second circuit and the plurality of analog storage cells; and a microcontroller coupled to the interface circuit that controls the sampling and storage of the analog signal and the reading of the stored samples, the microcontroller providing the addresses of the stored samples prior to reading of the stored samples, the microcontroller also providing addresses of the analog storage cells that are available for storage of samples of the analog signal.
Claim 23
Dependent Claim
146 words
A nonvolatile integrated circuit analog storage device having the capability of receiving, repetitively sampling, storing and reproducing an analog input signal comprising: a first circuit that samples an analog signal; a plurality of analog storage cells coupled to the first circuit, that stores samples of the analog signal; a second circuit that reads out the stored samples of the analog signal to reconstruct the analog signal; an interface circuit coupled to the first circuit, the second circuit and the plurality of analog storage cells; and a microcontroller coupled to the interface circuit that controls the sampling and storage of the analog signal and the reading of the stored samples, the microcontroller providing the addresses of the stored samples prior to reading of the stored samples, the microcontroller also providing addresses of the analog storage cells that are available for storage of samples of the analog signal.
Claim 24
Dependent Claim
38 words
The device of claim 20, wherein in a high speed read mode, the second circuit reads the stored samples, compares each stored sample with a reference voltage, and shifts out the result of the comparisons at high speed.
Claim 25
Dependent Claim
26 words
The device of claim 20, wherein the microcontroller provides a clock signal for synchronizing data transfer into the first circuit and out of the second circuit.
Claim 26
Dependent Claim
112 words
The device of claim 20, wherein the interface circuit comprises: an input shift register for receiving control and address information from the microcontroller; a logic circuit coupled to the input shift register for receiving the control information, the logic circuit generating an output signal in response to the control information; an address circuit coupled to the input shift register and to the logic circuit receiving the address information from the input shift register in response to the output signal; and an output shift register coupled to the logic circuit and to the address circuit, the address circuit providing the address information to the output shift register in response to the output signal.
Claim 27
Dependent Claim
25 words
The device of claim 22, wherein the control information and address information include information for initiating reading of the stored samples at a specified address.
Claim 28
Dependent Claim
26 words
The device of claim 22, wherein the control information and address information include information for initiating reading of the stored samples at a next available address.
Claim 29
Dependent Claim
102 words
The device of claim 20, wherein the input signal includes a first portion and a second portion, the device further comprising a fixed gain amplifier that has a first input terminal, a second input terminal and an output terminal, the first input terminal being coupled to receive the first portion of the input signal via a first resistor, the output terminal being coupled to the first input terminal via a second resistor, the second input terminal being coupled to receive the second portion via a third resistor, the second input terminal also being coupled to a ground terminal via a fourth signal.
Claim 30
Dependent Claim
19 words
The nonvolatile integrated circuit analog storage device of claim 26, wherein the input signal is a differential input signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-26 | 2002-04-27 | 2002-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-26 | 2006-04-27 | 2006-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-26 | 2010-04-27 | 2010-10-27 | $7700.00 | Window Closed / Lapsed |