US5828258A
Expired / Lapsed
US
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Semiconductor device and testing apparatus thereof
Assignee: Mitsubishi Electric Corp
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Filing: 1996-04-25
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Granted: 1998-10-27
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Expires: 2016-04-25
Abstract
Abstract A tester is connected to a signal output terminal provided in a DRAM chip, and a frequency of a clock signal output from an internal timer is monitored. The frequency of the clock signal is varied by changing the combination of 3 bit signals, so as to obtain signals by which the frequency closest to the set value is obtained. A fuse in the internal timer is disconnected to set the frequency of the clock signal so as to obtain the same state as in the case where that signal is applied.
Inventors
- 👤 Tsukasa Ooishi
- 👤 Tomoya Kawagoe
- 👤 Hideto Hidaka
- 👤 Mikio Asakura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:16
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C29/00; G11C29/02; G11C29/028; G11C11/4063; G11C11/407; G11C11/4076; G11C29/04; G11C29/50; G11C29/50012
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
86 words
A semiconductor device for performing a prescribed operation in synchronization with a clock signal, comprising, on a common chip: a clock generating circuit for generating said clock signal; an outputting terminal for drawing said clock signal output from said clock generating circuit externally of said chip; and switching means having one terminal for receiving said clock signal generated from said clock generating circuit and another terminal connected to said outputting terminal, wherein switching is activated in response to a control signal supplied externally of said chip.
Claim 2
Dependent Claim
86 words
A semiconductor device for performing a prescribed operation in synchronization with a clock signal, comprising, on a common chip: a clock generating circuit for generating said clock signal; an outputting terminal for drawing said clock signal output from said clock generating circuit externally of said chip; and switching means having one terminal for receiving said clock signal generated from said clock generating circuit and another terminal connected to said outputting terminal, wherein switching is activated in response to a control signal supplied externally of said chip.
Claim 3
Dependent Claim
85 words
A semiconductor device for performing a prescribed operation in synchronization with a clock signal, said semiconductor device comprising: an oscillator for producing the clock signal, the oscillator having a variable oscillation frequency; and a setting circuit capable of varying and setting the oscillation frequency of said oscillator, said setting circuit including a first portion for producing a binary address signal corresponding to a desired oscillation frequency, and a second portion for controlling said oscillator to operate at a frequency corresponding to said binary address signal.
Claim 4
Dependent Claim
85 words
A semiconductor device for performing a prescribed operation in synchronization with a clock signal, said semiconductor device comprising: an oscillator for producing the clock signal, the oscillator having a variable oscillation frequency; and a setting circuit capable of varying and setting the oscillation frequency of said oscillator, said setting circuit including a first portion for producing a binary address signal corresponding to a desired oscillation frequency, and a second portion for controlling said oscillator to operate at a frequency corresponding to said binary address signal.
Claim 5
Dependent Claim
60 words
The semiconductor device in accordance with claim 2, wherein said oscillator comprises: a plurality of inverters connected in a ring shape; a capacitance circuit provided corresponding to each inverter, connected to an output node of a corresponding inverter, said capacitance circuit having a variable capacitance value; and said setting circuit varies and sets the capacitance value of said capacitance circuit.
Claim 6
Dependent Claim
81 words
The semiconductor device in accordance with claim 3, wherein said oscillator further includes a transistor provided corresponding to each inverter and connected to at least one of a portion between a power supply node of the corresponding inverter and a power supply potential line and a portion between a ground node and a ground potential line, having its gate provided with an intermediate potential between a power supply potential and ground potential for suppressing a penetrating current of the corresponding inverter.
Claim 7
Dependent Claim
65 words
The semiconductor device in accordance with claim 3, wherein said capacitance circuit includes a plurality of sets of transfer gates and capacitors connected in series between an output node of the corresponding inverter and a prescribed potential line, and said setting means includes a fuse provided corresponding to each of the transfer gates for fixing a corresponding transfer gate at a conductive or non-conductive state.
Claim 8
Dependent Claim
21 words
The semiconductor device in accordance with claim 2, further comprising an output circuit externally drawing the clock signal from said oscillator.
Claim 9
Dependent Claim
91 words
The semiconductor device in accordance with claim 2, wherein said oscillator includes a plurality of inverters connected in a ring shape; a first transistor provided corresponding to each of the inverters, and connected between a power supply node of the corresponding inverter and a power supply potential line; and a second transistor provided corresponding to each of the inverters and connected between a ground node of the corresponding inverter and a ground potential line; and wherein said setting means changes and sets the input voltage of said first and second transistors.
Claim 10
Dependent Claim
97 words
The semiconductor device in accordance with claim 7, wherein said setting means includes a constant current source for causing a constant current to flow; a third transistor connected in series with said constant current source and forming a current mirror circuit with one of said first and second transistors; a plurality of fourth transistors connected in parallel with said third transistor, respectively, for dividing the flow of output current from said constant current source; and a fuse provided corresponding to each of the fourth transistors for fixing the corresponding fourth transistor at a conductive or non-conductive state.
Claim 11
Dependent Claim
82 words
The semiconductor device in accordance with claim 7, wherein said setting means includes a plurality of constant current sources for causing flow of constant current, respectively; a third transistor connected to an output node of each of said plurality of constant current sources for forming a current mirror circuit with one of said first and second transistors; and a fuse provided corresponding to each of the constant current sources for fixing the corresponding constant current source at an active or inactive state.
Claim 12
Dependent Claim
131 words
The semiconductor device in accordance with claim 2, further comprising: a plurality of signal converting means connected in series in which said clock signal output from said oscillator is input to a first stage and each of said plurality of signal converting means converts the clock signal input from its preceding stage to a clock signal having a period which is a plurality of times the period of the input clock signal and outputs the converted signal to the following stage; a selecting means for selecting one clock signal from said clock signal output from said oscillator and the plurality of clock signals output from said plurality of signal converting means; and an internal circuit for performing a prescribed operation in synchronization with the clock signal selected by said selecting means.
Claim 13
Dependent Claim
72 words
The semiconductor device in accordance with claim 10, wherein said selecting means includes a plurality of gate means provided corresponding to one of said oscillator and said plurality of signal converting means, respectively, to which the clock signal output from the corresponding oscillator or signal converting means is input; and a fuse provided corresponding to each of the gate means for fixing the corresponding gate means at a conductive or non-conductive state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-26 | 2002-04-27 | 2002-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-26 | 2006-04-27 | 2006-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-26 | 2010-04-27 | 2010-10-27 | $7700.00 | Window Closed / Lapsed |