Delay unit implemented by inverting circuits associated with capacitive load for increasing delay

Claim 2

A semiconductor device provided with a delay unit fabricated on a semiconductor substrate having a plurality of first active areas of one conductivity type and a plurality of second active areas of the opposite conductivity type respectively paired with said plurality of first active areas so as to form a plurality of active pairs, comprising: a) load circuit formed by a part of a first active area of one of said plurality of active pairs, a part of a second active area paired with said first active area and a predetermined polysilicon strip extending over said parts of said first and second active areas; and b) a plurality of complementary inverting circuits formed by additional polysilicon strips, active pairs selected from said plurality of active pairs and said predetermined polysilicon strip, other part of said first active area and other part of said second active area, and coupled in cascade, said plurality of complementary inverting circuits for producing a delayed signal in cooperation with said load circuit, said plurality of complementary inverting circuits having a first complementary inverting circuit supplied with an input signal and a final complementary inverting circuit outputting said delayed signal, one of said plurality of complementary inverting circuits except for said final complementary inverting circuit being formed by said other part of said first active area, said other part of said second active area and said predetermined polysilicon strip, said load circuit being coupled to an output node of another of said plurality of complementary inverting circuits except for said final complementary inverting circuit, said one of said plurality of complementary inverting circuits being larger in channel resistance than said another of said plurality of complementary inverting circuits.

Claim 3

A delay unit as set forth in claim 1, in which said plurality of first active areas and said plurality of second active areas are shaped into a generally rectangular configuration, and have reactive widths approximately equal to one another.

Claim 4

A delay unit as set forth in claim 2 in which said plurality of first active means and said plurality of second active areas are defined by a thick field oxide film, said thick field oxide film penetrating into said one of said plurality of first active areas and said one of said plurality of second active areas so that bifurcated portions each having two projections are formed therein, said load circuit being formed in association with one of the projections of one of said bifurcated portions and with one of the projections of the other bifurcated portion, said one of said plurality of complementary inverting circuits except for said final complementary inverting circuit being formed in association with the other projections of said respective bifurcated portions, said another of said plurality of complementary inverting circuits being formed in association with a remaining portion of said one of said plurality of first active areas and with a remaining portion of said one of said plurality of second active areas, said remaining portions being wider than said projections.

Claim 5

A delay unit as set forth in claim 3, in which said load circuit comprises load transistors each having said one of said projections of a respective bifurcated potion, a first insulating film covering a part of said one of said projections and a predetermined polysilicon strip passing over said first insulating film, parts of said one of said projections on both sides of said part beneath said first insulating film being electrically connected to each other.

Claim 6

A delay unit as set forth in claim 4, in which said one of said plurality of complementary inverting circuits except for said final complementary inverting circuit comprises a series combination of a first enhancement type field effect transistor and a second enhancement type field effect transistor opposite in channel conductivity type, said first enhancement type field effect transistor having a second insulating film covering a part of one of said other projections, source and drain regions formed in parts of said one of said other projections on both sides of said part beneath said second insulating film, and said predetermined polysilicon strip passing over said second insulating film, said second enhancement type field effect transistor having a third insulating film covering a part of the other of said other projections, source and drain regions formed in parts of said other of said other projections on both sides of said part beneath said third insulating film, and said predetermined polysilicon strip passing over said third insulating film.

Claim 7

A delay unit as set forth in claim 5, in which said another of said plurality of complementary inverting circuits comprises a series combination of a third enhancement type field effect transistor and a fourth enhancement type field effect transistor opposite in channel conductivity type, said third enhancement type transistor having a fourth insulating film covering a part of said remaining portion of said one of said plurality of first active areas, source and drain regions formed in parts of said remaining portion on both sides of said part beneath said forth insulating film, and a one of said additional polysilicon strips passing over said fourth insulating film, said fourth enhancement type transistor having a fifth insulating film covering a part of said remaining portion of said one of said plurality of second active areas, source and drain regions formed in parts of said remaining portion on both sides of said part beneath said fifth insulating film, and said one of said additional polysilicon strips passing over said fifth insulating film, said third and fourth enhancement type transistors being larger in channel width than said first and second enhancement transistors.

Claim 8

A delay unit as set forth in claim 6, in which said first conductive strip is approximately equal in width to said second conductive strip.

Claim 9

A delay unit as set forth in claim 6, in which said first conductive strip is larger in width than said second conductive strip.

Claim 10

A semicustom-made integrated circuit fabricated on a semiconductor substrate and having a plurality of function blocks, delay unit being formed in one of said function blocks having a plurality of generally rectangular first active areas of one conductivity type and a plurality of generally rectangular second active areas of the opposite conductivity type respectively paired with said plurality of first active areas so as to form a plurality of active paris, said plurality of generally rectangular first active areas and said plurality of generally rectangular second active areas being defined by a thick field oxide film, said plurality of generally rectangular first and second active areas being approximately equal in width, said thick field oxide film penetrating from a side edge of one of said plurality of generally rectangular first active areas into said one of said plurality of generally rectangular first active areas and from a side edge of one of said plurality of generally rectangular second active areas paired with said one of said plurality of generally rectangular first active areas into said one of said plurality of generally rectangular second active areas so as to form first bifurcated portions in said one of said plurality of generally rectangular first active areas and second bifurcated portions in said one of said plurality of generally rectangular second active areas, respectively, said delay unit comprising: a) load circuit formed by one of said first bifurcated portions, one of said second bifurcated portions and a predetermined polysilicon strip extending over said one of said first bifurcated portions and said one of said second bifurcated portions, and b) a plurality of complementary inverting circuits formed by others of said plurality of generally rectangular first active areas, others of said plurality of generally rectangular second active areas, additional polysilicon strips, said predetermined polysilicon strip, the other of said first bifurcated portions and the other of said second bifurcated portions, and coupled in cascade for producing a delayed signal in cooperation with said load circuit, said plurality of complementary inverting circuits having a first complementary inverting circuit supplied with an input signal and a final complementary inverting circuit outputting said delayed signal, one of said plurality of complementary inverting circuits except for said final complementary inverting circuit being formed by said other of said first bifurcated portions and with said other of said second bifurcated portions and said predetermined polysilicon strip, another of said plurality of complementary inverting circuits being formed of another of said plurality of generally rectangular first active areas, another of said one of said generally rectangular second active areas and one of said additional polysilicon strips, said one of said plurality of inverting circuits being larger in channel resistance than said another of said plurality of complementary inverting circuits.

Claim 11

A semicustom-made integrated circuit fabricated on a semiconductor substrate and having a plurality of function blocks, delay unit being formed in one of said function blocks having a plurality of generally rectangular first active areas of one conductivity type and a plurality of generally rectangular second active areas of the opposite conductivity type respectively paired with said plurality of first active areas so as to form a plurality of active paris, said plurality of generally rectangular first active areas and said plurality of generally rectangular second active areas being defined by a thick field oxide film, said plurality of generally rectangular first and second active areas being approximately equal in width, said thick field oxide film penetrating from a side edge of one of said plurality of generally rectangular first active areas into said one of said plurality of generally rectangular first active areas and from a side edge of one of said plurality of generally rectangular second active areas paired with said one of said plurality of generally rectangular first active areas into said one of said plurality of generally rectangular second active areas so as to form first bifurcated portions in said one of said plurality of generally rectangular first active areas and second bifurcated portions in said one of said plurality of generally rectangular second active areas, respectively, said delay unit comprising: a) load circuit formed by one of said first bifurcated portions, one of said second bifurcated portions and a predetermined polysilicon strip extending over said one of said first bifurcated portions and said one of said second bifurcated portions, and b) a plurality of complementary inverting circuits formed by others of said plurality of generally rectangular first active areas, others of said plurality of generally rectangular second active areas, additional polysilicon strips, said predetermined polysilicon strip, the other of said first bifurcated portions and the other of said second bifurcated portions, and coupled in cascade for producing a delayed signal in cooperation with said load circuit, said plurality of complementary inverting circuits having a first complementary inverting circuit supplied with an input signal and a final complementary inverting circuit outputting said delayed signal, one of said plurality of complementary inverting circuits except for said final complementary inverting circuit being formed by said other of said first bifurcated portions and with said other of said second bifurcated portions and said predetermined polysilicon strip, another of said plurality of complementary inverting circuits being formed of another of said plurality of generally rectangular first active areas, another of said one of said generally rectangular second active areas and one of said additional polysilicon strips, said one of said plurality of inverting circuits being larger in channel resistance than said another of said plurality of complementary inverting circuits.

Claim 12

A semicustom-made integrated circuit as set forth in claim 9, in which said load circuit comprises load transistors each formed of said one of said first bifurcated portions, a first insulating film covering a part of said one of said first bifurcated portions and a predetermined polysilicon strip passing over said first insulating film, parts of said one of said first bifurcated portions on both sides of said part beneath said first insulating film being electrically connected to each other.

Claim 13

A semicustom-made integrated circuit as set forth in claim 10, in which said one of said plurality of complementary inverting circuits except for said final complementary inverting circuit comprises a series combination of a first enhancement type field effect transistor and a second enhancement type field effect transistor opposite in channel conductivity type, said first enhancement type field effect transistor having a second insulating film covering a part of the other of said first bifurcated portions, source and drain regions formed in parts of said other of said first bifurcated portions on both sides of said part beneath said second insulating film, and said predetermined polysilicon strip passing over said second insulating film, said second enhancement type field effect transistor having a third insulating film covering a part of the other of said second bifurcated portions, source and drain regions formed in parts of said second bifurcated portions on both sides of said part beneath said third insulating film, and said predetermined polysilicon strip passing over said third insulating film.

Claim 14

A semicustom-made integrated circuit as set forth in claim 11, in which said another of said plurality of complementary inverting circuits comprises a series combination of a third enhancement type field effect transistor and a fourth enhancement type field effect transistor opposite in channel conductivity type, said third enhancement type transistor having a fourth insulating film covering a part of said remaining portion of said one of said plurality of first active areas, source and drain regions formed in parts of said remaining portion on both sides of said part beneath said forth insulating film, and a one of said additional polysilicon strips passing over said fourth insulating film, said fourth enhancement type transistor having a fifth insulating film covering a part of said remaining portion of said one of said plurality of second active areas, source and drain regions formed in parts of said remaining portion on both sides of said part beneath said fifth insulating film, and said one of said additional polysilicon strips passing over said fifth insulating film, said third and fourth enhancement type transistors being larger in channel width than said first and second enhancement transistors.

Claim 15

A semicustom-made integrated circuit as set forth in claim 12, in which said first conductive strip is approximately equal in width to said second conductive strip.

Claim 16

A semicustom-made integrated circuit as set forth in claim 12, in which said first conductive strip is larger in width than said second conductive strip.