US5097159A
Expired / Lapsed
US
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Delay circuit for delaying an output signal relative to an input signal for a specified time interval
Assignee: Fujitsu VLSI Ltd
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Filing: 1989-02-21
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Granted: 1992-03-17
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Expires: 2009-02-21
Abstract
Abstract A delay circuit having two or more first switching transistors connected in series between an output terminal and a power source line, and two or more second switching transistors connected in series between the output terminal and another power source line, the first and the second switching transistors operating in a complementary manner in response to an input signal, one or more nodes of each switching transistor being connected by one or more current paths each connecting at least one capacitor, whereby an input signal is transmitted to the output terminal at a specified interval defined by the capacitance of the capacitor.
Inventors
- 👤 Teruo Seki
- 👤 Akihiro Iwase
- 👤 Sinzi Nagai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 11:29
CPC Classifications
H; H03; H03H; H03H11/00; H03H11/02; H03H11/26; H03K; H03K5/00; H03K5/13; H03K5/133; H03K2005/00013; H03K2005/0015; H03K2005/00195; H03K2005/00215
Claims Analysis
Total Claims: 46
Claim 1
Independent Claim
168 words
A delay circuit comprising: a first switching transistor and a second switching transistor operating in a complementary manner in response to an input signal; an output terminal connected to a node commonly connected to said first switching transistor and said second switching transistor; at least one switching transistor of the same type as said first switching transistor provided between said first transistor and a power source line; at least one switching transistor of the same type as said second switching transistor provided between said second transistor and another power source line; at least one current path connecting at least one pair of nodes, wherein at least one node of said pair of nodes being connected by said at least one current path is located between said first switching transistor and said power source line, and wherein another node of said pair of nodes is located between said second switching transistor and said another power source line; at least one capacitor connected to said at least one current path.
Claim 2
Dependent Claim
168 words
A delay circuit comprising: a first switching transistor and a second switching transistor operating in a complementary manner in response to an input signal; an output terminal connected to a node commonly connected to said first switching transistor and said second switching transistor; at least one switching transistor of the same type as said first switching transistor provided between said first transistor and a power source line; at least one switching transistor of the same type as said second switching transistor provided between said second transistor and another power source line; at least one current path connecting at least one pair of nodes, wherein at least one node of said pair of nodes being connected by said at least one current path is located between said first switching transistor and said power source line, and wherein another node of said pair of nodes is located between said second switching transistor and said another power source line; at least one capacitor connected to said at least one current path.
Claim 3
Dependent Claim
16 words
A delay circuit as set forth in claim 1, wherein said current path has a resistance.
Claim 4
Dependent Claim
34 words
A delay circuit as set forth in claim 2, wherein a single capacitor is connected to said current path and a free terminal is connected to a power source line having a predetermined potential.
Claim 5
Dependent Claim
25 words
A delay circuit as set forth in claim 3, further comprising resistors connected to said capacitor in said current path, said resistors providing said resistance.
Claim 6
Dependent Claim
20 words
A delay circuit as set forth in claim 4, wherein said power source line is a positive power source line.
Claim 7
Dependent Claim
20 words
A delay circuit as set forth in claim 4, wherein said power source line is a negative power source line.
Claim 8
Dependent Claim
29 words
A delay circuit as set forth in claim 1, wherein free terminals of said at least one capacitor are connected to a power source line having a predetermined potential.
Claim 9
Dependent Claim
53 words
A delay circuit as set forth in claim 1, wherein two capacitors are connected to said current paths respectively, wherein each of said current paths shares a predetermined resistance connected between said two capacitors, and each of said free terminals is connected to a different power source line having a different predetermined potential.
Claim 10
Dependent Claim
27 words
A delay circuit as set forth in claim 8, wherein said different power source lines are a positive power source line and a negative power source line.
Claim 11
Dependent Claim
22 words
A delay circuit as set forth in claim 8, further comprising a resistor in said current path for providing said predetermined resistance.
Claim 12
Dependent Claim
27 words
A delay circuit as set forth in claim 10, wherein said different power source lines are a positive power source line and a negative power source line.
Claim 13
Dependent Claim
33 words
A delay circuit as set forth in claim 1, wherein said capacitor is connected in parallel to said current path, and wherein said current path parallel to said capacitor has a predetermined resistance.
Claim 14
Dependent Claim
22 words
A delay circuit as set forth in claim 12, further comprising a resistor in said current path for providing said predetermined resistance.
Claim 15
Dependent Claim
124 words
A delay circuit as set forth in claim 1, wherein a single switching transistor of the same type as said first switching transistor is provided between said first transistor and a power source line, a single switching transistor of the same type as said second switching transistor is provided between said second transistor and another power source line, and a single current path connects a pair of nodes, one of said pair of nodes being located between said first switching transistor and said single switching transistor of the same type as said first switching transistor and the other of said pair of nodes being located between said second switching transistor and said single switching transistor of the same type as said second switching transistor.
Claim 16
Dependent Claim
57 words
A delay circuit as set forth in claim 14, wherein two capacitors are respectively connected, one each to said single current path, wherein each of said current paths shares a predetermined resistance connected between said two capacitors, and a different power source line having a different predetermined potential is respectively connected to a different power source line.
Claim 17
Dependent Claim
27 words
A delay circuit as set forth in claim 15, wherein said different power source lines are a positive power source line and a negative power source line.
Claim 18
Dependent Claim
23 words
A delay circuit as set forth in claim 15, further comprising a resistor provided in said current path for providing said predetermined resistance.
Claim 19
Dependent Claim
27 words
A delay circuit as set forth in claim 17, wherein said different power source lines are a positive power source line and a negative power source line.
Claim 20
Dependent Claim
34 words
A delay circuit as set forth in claim 14, wherein a single capacitor is connected to said current path and a free terminal is connected to a power source line having a predetermined potential.
Claim 21
Dependent Claim
16 words
A delay circuit as set forth in claim 19, wherein said current path has a resistance.
Claim 22
Dependent Claim
26 words
A delay circuit as set forth in claim 20, further comprising resistors connected to said capacitor in said current path, said resistors providing said predetermined resistance.
Claim 23
Dependent Claim
20 words
A delay circuit as set forth in claim 19, wherein said power source line is a positive power source line.
Claim 24
Dependent Claim
16 words
A delay circuit as set forth in claim 22, wherein said current path has a resistance.
Claim 25
Dependent Claim
25 words
A delay circuit as set forth in claim 23, further comprising resistors connected to said capacitor in said current path, said resistors providing said resistance.
Claim 26
Dependent Claim
20 words
A delay circuit as set forth in claim 19, wherein said power source line is a negative power source line.
Claim 27
Dependent Claim
16 words
A delay circuit as set forth in claim 25, wherein said current path has a resistance.
Claim 28
Dependent Claim
25 words
A delay circuit as set forth in claim 26, further comprising resistors connected to said capacitor in said current path, said resistors providing said resistance.
Claim 29
Dependent Claim
37 words
A delay circuit as set forth in claim 14, wherein said capacitor is connected in parallel to said current path, and wherein a portion of said current path in parallel to said capacitor has a predetermined resistance.
Claim 30
Dependent Claim
21 words
A delay circuit as set forth in claim 28, further comprising a resistor in said current path for providing said resistance.
Claim 31
Dependent Claim
109 words
A delay circuit as set forth in claim 1, wherein two switching transistors of the same type as first switching transistor are provided between said first transistor and a power source line, two switching transistors of the same type as said second switching transistor are provided between said second transistor and another power source line, and at least one current path connected to said each of said pair of nodes, one of said pair of nodes being located between said first switching transistor and said power source line and the other of said pair of nodes being located between said second switching transistor and said another power source line.
Claim 32
Dependent Claim
57 words
A delay circuit as set forth in claim 30, wherein two capacitors re connected to said current paths respectively, wherein each of said current paths between points at which said two capacitors are connected has a predetermined resistance, and each of said free terminals is connected to a different power source line having a different predetermined potential.
Claim 33
Dependent Claim
27 words
A delay circuit as set forth in claim 31, wherein said different power source lines are a positive power source line and a negative power source line.
Claim 34
Dependent Claim
22 words
A delay circuit as set forth in claim 31, further comprising a resistor in said current path for providing said predetermined resistance.
Claim 35
Dependent Claim
27 words
A delay circuit as set forth in claim 33, wherein said different power sourced lines are a positive power source line and a negative power source line.
Claim 36
Dependent Claim
35 words
A delay circuit as set forth in claim 30, wherein a single capacitor is connected to said current path respectively and a free terminal is connected to a power source line having a predetermined potential.
Claim 37
Dependent Claim
16 words
A delay circuit as set forth in claim 35, wherein said current path has a resistance.
Claim 38
Dependent Claim
24 words
A delay circuit as set forth in claim 36, wherein said resistance is provided by resistors connected to said capacitor in said current path.
Claim 39
Dependent Claim
20 words
A delay circuit as set forth in claim 35, wherein said power source line is a positive power source line.
Claim 40
Dependent Claim
16 words
A delay circuit as set forth in claim 38, wherein said current path has a resistance.
Claim 41
Dependent Claim
25 words
A delay circuit as set forth in claim 39, further comprising resistors connected to said capacitor in said current path, said resistors providing said resistance.
Claim 42
Dependent Claim
20 words
A delay circuit as set forth in claim 35, wherein said power source line is a negative power source line.
Claim 43
Dependent Claim
16 words
A delay circuit as set forth in claim 41, wherein said current path has a resistance.
Claim 44
Dependent Claim
25 words
A delay circuit as set forth in claim 42, further comprising resistors connected to said capacitor in said current path, said resistors providing said resistance.
Claim 45
Dependent Claim
37 words
A delay circuit as set forth in claim 30, wherein said capacitor is connected in parallel to said current path, and wherein a portion of said current path in parallel to said capacitor has a predetermined resistance.
Claim 46
Dependent Claim
22 words
A delay circuit as set forth in claim 44, further comprising a resistors provided in said current path for providing said resistance.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-17 | 1995-09-16 | 1996-03-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-17 | 1999-09-16 | 2000-03-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-17 | 2003-09-16 | 2004-03-17 | $7700.00 | Window Closed / Lapsed |