Abstract A buried bit line cell and a manufacturing method thereof increases the integration density of a semiconductor device such as a DRAM. The semiconductor device includes: a semiconductor substrate having a plurality of spaced apart first pillars formed therein with isolated first trenches therebetween and second pillars connected to the first pillars thereunder with isolated second trenches therebetween; a first isolation insulating layer formed inside the first trenches and isolated by a gate insulating layer and gate electrode enclosing the first pillars; impurity-doped regions having a first and second impurity-doped region vertically formed in the first and second pillars and a channel region therebetween; a bit line formed in the bottom and on the sidewalls of the second trenches and connected to the impurity-doped regions; a second isolation insulating layer formed in the bottom of the first trenches and inside the second trenches, for isolating the bit lines; and a word line isolated by the first isolation insulating layer and connected to the gate electrode. Problems due to a deep trench and step formation are resolved by controlling the height of the first and second pillars and the storage node of a capacitor.
Inventors
👤 Joo-young Lee
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-11-07 10:33
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/34
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
165 words
A semiconductor device, comprising: a semiconductor substrate having a plurality of spaced apart first pillars formed therein with isolated first trenches therebetween and second pillars connected to said first pillars thereunder with isolated second trenches therebetween, a width of said second trenches being smaller than a width of said first trenches; a first isolation insulating layer formed inside said first trenches and isolated by a gate insulating layer and gate electrode enclosing said first pillars; impurity-doped regions having a first and a second impurity-doped region vertically formed in said first and second pillars and a channel region therebetween; a bit line surrounding said second pillars and connected to said first impurity-doped region, said bit line being formed as a matrix type with said gate electrode; a second isolation insulating layer formed in the bottom of said first trenches and inside said second trenches, for isolating said bit lines; and a word line isolated by said first isolation insulating layer and connected to said gate electrode.
Claim 2
Dependent Claim
165 words
A semiconductor device, comprising: a semiconductor substrate having a plurality of spaced apart first pillars formed therein with isolated first trenches therebetween and second pillars connected to said first pillars thereunder with isolated second trenches therebetween, a width of said second trenches being smaller than a width of said first trenches; a first isolation insulating layer formed inside said first trenches and isolated by a gate insulating layer and gate electrode enclosing said first pillars; impurity-doped regions having a first and a second impurity-doped region vertically formed in said first and second pillars and a channel region therebetween; a bit line surrounding said second pillars and connected to said first impurity-doped region, said bit line being formed as a matrix type with said gate electrode; a second isolation insulating layer formed in the bottom of said first trenches and inside said second trenches, for isolating said bit lines; and a word line isolated by said first isolation insulating layer and connected to said gate electrode.
Claim 3
Dependent Claim
35 words
A semiconductor device as claimed in claim 1, further comprising a stack-structured capacitor having a storage node, dielectric layer and plate electrode, said stack-structured capacitor being wrapped around the top portion of said first pillars.
Claim 4
Dependent Claim
19 words
A semiconductor device as claimed in claim 2 wherein said stack-structured capacitor is a pin or cylinder type capacitor.
Claim 5
Dependent Claim
24 words
A semiconductor device as claimed in claim 2 wherein said storage node and said word line are isolated by said first isolation insulating layer.
Claim 6
Dependent Claim
30 words
A semiconductor device as claimed in claim 1 wherein said impurity-doped regions and said channel region are a vertical transistor formed on the surface of said first and second pillars.