Patent US5826089A successfully refreshed from Google Patents.
US5826089A
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US
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Instruction translation unit configured to translate from a first instruction set to a second instruction set
Assignee: RPX Corp
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Filing: 1996-01-04
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Granted: 1998-10-20
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Expires: 2016-01-04
Abstract
Abstract An instruction translation unit is provided which reduces instructions from a source instruction set to a set of intermediate, atomic operations. The atomic operations are then recombined into instructions in the target instruction set. An execution core coupled to the instruction translation unit may be configured to execute instructions from the target instruction set. However, compatibility with the source instruction set is maintained. By reducing a plurality of source instructions into atomic operations, portions of multiple source instructions may be combined into a target instructions. The execution core may thereby be more efficiently utilized.
Inventors
- 👤 Mark A. Ireton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 15:06
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3818; G06F9/382; G06F9/3017; G06F9/30174; G06F9/30181; G06F9/3802; G06F9/3808; G06F9/3836; G06F9/3838; G06F9/384; G06F9/3853; G06F9/3885
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
184 words
A microprocessor comprising: an instruction cache configured to store instructions from a first instruction set and instructions from a second instruction set, wherein each instruction stored within the instruction cache includes an indication of whether the instruction belongs to said first instruction set or said second instruction set; an instruction translation unit coupled to receive a first instruction belonging to said first instruction set from the instruction cache, said instruction translation unit comprising: an instruction atomizing unit configured to generate a plurality of intermediate operations corresponding to said first instruction; and an instruction recombination unit coupled to receive said plurality of intermediate operations and to combine one or more of said plurality of intermediate operations into a second instruction from said second instruction set; and an execution core coupled to receive from said instruction cache said instructions from said second instruction set, and coupled to receive said second instruction from said instruction translation unit; wherein said instruction cache is configured to selectively provide each instruction stored within said instruction cache to either said instruction translation unit or said execution core depending upon said indication.
Claim 2
Dependent Claim
184 words
A microprocessor comprising: an instruction cache configured to store instructions from a first instruction set and instructions from a second instruction set, wherein each instruction stored within the instruction cache includes an indication of whether the instruction belongs to said first instruction set or said second instruction set; an instruction translation unit coupled to receive a first instruction belonging to said first instruction set from the instruction cache, said instruction translation unit comprising: an instruction atomizing unit configured to generate a plurality of intermediate operations corresponding to said first instruction; and an instruction recombination unit coupled to receive said plurality of intermediate operations and to combine one or more of said plurality of intermediate operations into a second instruction from said second instruction set; and an execution core coupled to receive from said instruction cache said instructions from said second instruction set, and coupled to receive said second instruction from said instruction translation unit; wherein said instruction cache is configured to selectively provide each instruction stored within said instruction cache to either said instruction translation unit or said execution core depending upon said indication.
Claim 3
Dependent Claim
48 words
The microprocessor as recited in claim 1 wherein the execution core is configured to execute instructions from said second instruction set received from said instruction cache, and wherein said execution core is further configured to execute recombined instructions generated by said instruction translation unit including said second instruction.
Claim 4
Dependent Claim
40 words
The microprocessor as recited in claim 1 further comprising a dependency checking unit coupled between said instruction atomizing unit and said instruction recombination unit, wherein said dependency checking unit is configured to detect dependencies between said plurality of intermediate operations.
Claim 5
Dependent Claim
45 words
The microprocessor as recited in claim 3 wherein said instruction recombination unit is configured not to combine one of said plurality of intermediate operations with another one of said plurality of intermediate operations upon which said one of said plurality of intermediate operations is dependent.
Claim 6
Dependent Claim
198 words
A computer system, comprising: a main memory configured to store instructions from a first instruction set and instructions from a second instruction set; and a microprocessor coupled to said main memory, wherein said microprocessor comprises: an instruction cache configured to store the instructions from said first instruction set and the instructions from the said second instruction set, wherein each instruction stored within the instruction cache includes an indication of whether the instruction belongs to said first instruction set or said second instruction set; an instruction translation unit coupled to receive a first instruction belonging to said first instruction set from said instruction cache, wherein said instruction translation unit is configured to reduce said first instruction to a plurality of intermediate operations and to recombine said plurality of intermediate operations into a second instruction from said second instruction set; and an execution core coupled to receive from said instruction cache said instructions from said second instruction set, and coupled to receive said second instruction from said instruction translation unit; wherein said instruction cache is configured to selectively provide each instruction stored within said instruction cache to either said instruction translation unit or said execution core depending upon said indication.
Claim 7
Dependent Claim
198 words
A computer system, comprising: a main memory configured to store instructions from a first instruction set and instructions from a second instruction set; and a microprocessor coupled to said main memory, wherein said microprocessor comprises: an instruction cache configured to store the instructions from said first instruction set and the instructions from the said second instruction set, wherein each instruction stored within the instruction cache includes an indication of whether the instruction belongs to said first instruction set or said second instruction set; an instruction translation unit coupled to receive a first instruction belonging to said first instruction set from said instruction cache, wherein said instruction translation unit is configured to reduce said first instruction to a plurality of intermediate operations and to recombine said plurality of intermediate operations into a second instruction from said second instruction set; and an execution core coupled to receive from said instruction cache said instructions from said second instruction set, and coupled to receive said second instruction from said instruction translation unit; wherein said instruction cache is configured to selectively provide each instruction stored within said instruction cache to either said instruction translation unit or said execution core depending upon said indication.
Claim 8
Dependent Claim
49 words
The computer system as recited in claim 5 wherein said execution core is configured to execute instructions from said second instruction set received from said instruction cache, and wherein said execution core is further configured to execute recombined instructions generated by said instruction translation unit including said second instruction.
Claim 9
Dependent Claim
191 words
A microprocessor comprising: an instruction cache configured to store instructions from a first instruction set and instructions from a second instruction set, wherein each instruction stored within the instruction cache includes an indication of whether the instruction belongs to said first instruction set or said second instruction set; an instruction translation unit coupled to receive a first plurality of instructions belonging to said first instruction set from the instruction cache, said instruction translation unit comprising: an instruction atomizing unit configured to generate a plurality of intermediate operations corresponding to said first plurality of instructions; and an instruction recombination unit coupled to receive said plurality of intermediate operations and to combine said plurality of intermediate operations corresponding to said first plurality of instructions into a second instruction from said second instruction set; and an execution core coupled to receive from said instruction cache said instructions from said second instruction set, and coupled to receive said second instruction from said instruction translation unit; wherein said instruction cache is configured to selectively provide each instruction stored within said instruction cache to either said instruction translation unit or said execution core depending upon said indication.
Claim 10
Dependent Claim
191 words
A microprocessor comprising: an instruction cache configured to store instructions from a first instruction set and instructions from a second instruction set, wherein each instruction stored within the instruction cache includes an indication of whether the instruction belongs to said first instruction set or said second instruction set; an instruction translation unit coupled to receive a first plurality of instructions belonging to said first instruction set from the instruction cache, said instruction translation unit comprising: an instruction atomizing unit configured to generate a plurality of intermediate operations corresponding to said first plurality of instructions; and an instruction recombination unit coupled to receive said plurality of intermediate operations and to combine said plurality of intermediate operations corresponding to said first plurality of instructions into a second instruction from said second instruction set; and an execution core coupled to receive from said instruction cache said instructions from said second instruction set, and coupled to receive said second instruction from said instruction translation unit; wherein said instruction cache is configured to selectively provide each instruction stored within said instruction cache to either said instruction translation unit or said execution core depending upon said indication.
Claim 11
Dependent Claim
48 words
The microprocessor as recited in claim 7 wherein the execution core is configured to execute instructions from said second instruction set received from said instruction cache, and wherein said execution core is further configured to execute recombined instructions generated by said instruction translation unit including said second instruction.
Claim 12
Dependent Claim
40 words
The microprocessor as recited in claim 7 further comprising a dependency checking unit coupled between said instruction atomizing unit and said instruction recombination unit, wherein said dependency checking unit is configured to detect dependencies between said plurality of intermediate operations.
Claim 13
Dependent Claim
45 words
The microprocessor as recited in claim 9 wherein said instruction recombination unit is configured not to combine one of said plurality of intermediate operations with another one of said plurality of intermediate operations upon which said one of said plurality of intermediate operations is dependent.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-19 | 2002-04-20 | 2002-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-19 | 2006-04-20 | 2006-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-19 | 2010-04-20 | 2010-10-20 | $7700.00 | Window Closed / Lapsed |