US5619665A
Expired / Lapsed
US
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Method and apparatus for the transparent emulation of an existing instruction-set architecture by an arbitrary underlying instruction-set architecture
Assignee: International Business Machines Corp
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Filing: 1995-04-13
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Granted: 1997-04-08
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Expires: 2015-04-13
Abstract
Abstract The invention provides means and methods for extending an instruction-set architecture without impacting the software interface. This circumvents all software compatibility issues, and allows legacy software to benefit from new architectural extensions without recompilation and reassembly. The means employed are a translation engine for translating sequences of old architecture instructions into primary, new architecture instructions, and an extended instruction (EI) cache memory for storing the translations. A processor requesting a sequence of instructions will look first to the EI-cache for a translation, and if translations are unavailable, will look to a conventional cache memory for the sequence, and finally, if still unavailable, will look to a main memory.
Inventors
- 👤 Philip G. Emma
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 13:37
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3808; G06F9/3017; G06F9/30174; G06F9/44; G06F9/455; G06F9/45504
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
133 words
A method for translating a series of one or more instructions of a first semantic type into one or more instructions of a second semantic type, comprising the steps of: providing a first memory; providing a second memory; translating a sequence of instructions of the first semantic type stored in the first memory into one or more primary instructions of the second semantic type and storing the instructions of the second type in the second memory; upon a request from the processor for the sequence of instructions of the first semantic type: providing the corresponding instructions of the second semantic type if available in the second memory; providing the sequence of instructions of the first semantic type if the corresponding instructions of the second semantic type are not available in the second memory.
Claim 2
Independent Claim
133 words
A method for translating a series of one or more instructions of a first semantic type into one or more instructions of a second semantic type, comprising the steps of: providing a first memory; providing a second memory; translating a sequence of instructions of the first semantic type stored in the first memory into one or more primary instructions of the second semantic type and storing the instructions of the second type in the second memory; upon a request from the processor for the sequence of instructions of the first semantic type: providing the corresponding instructions of the second semantic type if available in the second memory; providing the sequence of instructions of the first semantic type if the corresponding instructions of the second semantic type are not available in the second memory.
Claim 3
Dependent Claim
24 words
The method of claim 1, further comprising: providing a third memory; storing the sequence of instructions of the first type in the third memory.
Claim 4
Dependent Claim
29 words
The method of claim 2, wherein the step of translating is performed before moving one or more instructions of the first type from the third memory to the processor.
Claim 5
Dependent Claim
23 words
The method of claim 3, wherein the step of translation is performed after instructions are moved from the third memory to the processor.
Claim 6
Dependent Claim
19 words
The method of claim 1, wherein the translation is performed prior to the request for the sequence of instructions.
Claim 7
Dependent Claim
27 words
The method of claim 2, wherein the step of providing the sequence of instructions of the first type to the processor is performed by the third memory.
Claim 8
Dependent Claim
28 words
The method of claim 6, wherein the processor requests the sequence of instructions by sending an address signal to the second and third memory via an address bus.
Claim 9
Dependent Claim
13 words
The method of claim 4, wherein the second memory is a storage queue.
Claim 10
Independent Claim
112 words
An apparatus, comprising: a first memory; a second memory; a processor; means for translating a sequence of instructions of a first semantic type stored in the first memory into one or more instructions of a second semantic type and for storing the instructions of the second type in the second memory; means, upon a request from the processor for the sequence of instructions of the first semantic type: for providing the corresponding instructions of the second semantic type if available in the second memory; and for providing the sequence of instructions of the first semantic type if the corresponding instructions of the second semantic type are not available in the second memory.
Claim 11
Independent Claim
112 words
An apparatus, comprising: a first memory; a second memory; a processor; means for translating a sequence of instructions of a first semantic type stored in the first memory into one or more instructions of a second semantic type and for storing the instructions of the second type in the second memory; means, upon a request from the processor for the sequence of instructions of the first semantic type: for providing the corresponding instructions of the second semantic type if available in the second memory; and for providing the sequence of instructions of the first semantic type if the corresponding instructions of the second semantic type are not available in the second memory.
Claim 12
Dependent Claim
14 words
The apparatus of claim 9, wherein the means for translating is a translation engine.
Claim 13
Dependent Claim
42 words
The apparatus of claim 10, wherein the translation engine is coupled between the first memory and the second memory, and the means for delivering the primary instruction to the processor comprises a first data bus coupling the second memory and the processor.
Claim 14
Dependent Claim
30 words
The apparatus of claim 11, further comprising a third memory coupled to the first memory via a second data bus, and coupled to the processor by a third data bus.
Claim 15
Dependent Claim
31 words
The apparatus of claim 12, wherein the third memory is coupled to the translation engine via the third data bus, the third data bus constituting an input to the translation engine.
Claim 16
Dependent Claim
31 words
The apparatus of claim 13, wherein the translation engine is coupled to the second memory via a fourth data bus, the fourth data bus comprising an input to the second memory.
Claim 17
Dependent Claim
31 words
The apparatus of claim 12, wherein the translation engine is coupled to the first memory via the second data bus, the second data bus comprising an input to the translation engine.
Claim 18
Dependent Claim
19 words
The apparatus of claim 12, further comprising means for fetching an instruction prior to the processor requesting the instruction.
Claim 19
Dependent Claim
20 words
The apparatus of claim 16, wherein the means for fetching comprises a branch history table coupled to the translation engine.
Claim 20
Dependent Claim
19 words
The apparatus of claim 9, wherein the first memory is a system main memory having a first access speed.
Claim 21
Dependent Claim
28 words
The apparatus of claim 18, wherein the second memory is an extended instruction cache memory having an access speed faster than the access speed of the main memory.
Claim 22
Dependent Claim
13 words
The apparatus of claim 18, wherein the second memory is an instruction queue.
Claim 23
Independent Claim
174 words
An apparatus, comprising: a main memory; an instruction cache memory coupled to the main memory via a first bus; a processor coupled to the instruction cache memory via a second bus; an address bus connecting the processor and the instruction cache memory for delivering instruction request signals from the processor to the instruction cache; means responsive to the instruction request signals for transferring requested instructions from the instruction cache memory to the processor if the requested instructions are stored in the instruction cache memory; means responsive to the instruction request signal for transferring the requested instructions from the main memory to the processor via the instruction cache memory if the requested instructions are not stored in the instruction cache memory; a translation engine coupled to receive instructions output from the instruction cache memory via the second bus; a storage unit coupled to receive translated instructions corresponding to the requested instructions from the translation engine; means responsive to the instruction request signal for transferring the translated instructions stored in the storage unit to the processor.
Claim 24
Independent Claim
174 words
An apparatus, comprising: a main memory; an instruction cache memory coupled to the main memory via a first bus; a processor coupled to the instruction cache memory via a second bus; an address bus connecting the processor and the instruction cache memory for delivering instruction request signals from the processor to the instruction cache; means responsive to the instruction request signals for transferring requested instructions from the instruction cache memory to the processor if the requested instructions are stored in the instruction cache memory; means responsive to the instruction request signal for transferring the requested instructions from the main memory to the processor via the instruction cache memory if the requested instructions are not stored in the instruction cache memory; a translation engine coupled to receive instructions output from the instruction cache memory via the second bus; a storage unit coupled to receive translated instructions corresponding to the requested instructions from the translation engine; means responsive to the instruction request signal for transferring the translated instructions stored in the storage unit to the processor.
Claim 25
Dependent Claim
14 words
The apparatus of claim 21, wherein the stored unit is a first-in, first-out buffer.
Claim 26
Independent Claim
164 words
An apparatus, comprising: a main memory; an instruction cache memory coupled to receive outputs from the main memory; a translation engine coupled to receive outputs from the main memory; an extended instruction cache coupled to receive outputs from the translation engine; a processor coupled to receive outputs from the instruction cache and from the extended instruction cache; means for delivering instruction request signals from the processor to the instruction cache and to the extended instruction cache; means for translating a plurality of instructions, conveyed to the translation engine via the second bus, into one or more primary instructions; means for storing the plurality of instructions in the instruction cache; means responsive to the instruction request signal for conveying the one or more primary instructions to the processor, if the primary instructions exist; means responsive to the instruction request signal for conveying the plurality of instructions from the instruction cache memory to the processor if no primary instruction corresponding to the plurality of instructions exists.
Claim 27
Independent Claim
164 words
An apparatus, comprising: a main memory; an instruction cache memory coupled to receive outputs from the main memory; a translation engine coupled to receive outputs from the main memory; an extended instruction cache coupled to receive outputs from the translation engine; a processor coupled to receive outputs from the instruction cache and from the extended instruction cache; means for delivering instruction request signals from the processor to the instruction cache and to the extended instruction cache; means for translating a plurality of instructions, conveyed to the translation engine via the second bus, into one or more primary instructions; means for storing the plurality of instructions in the instruction cache; means responsive to the instruction request signal for conveying the one or more primary instructions to the processor, if the primary instructions exist; means responsive to the instruction request signal for conveying the plurality of instructions from the instruction cache memory to the processor if no primary instruction corresponding to the plurality of instructions exists.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-07 | 2000-10-07 | 2001-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-07 | 2004-10-07 | 2005-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-07 | 2008-10-07 | 2009-04-08 | $7700.00 | Window Closed / Lapsed |