Patent US5825878A successfully refreshed from Google Patents.
US5825878A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Secure memory management unit for microprocessor
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1996-09-20
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Granted: 1998-10-20
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Expires: 2016-09-20
Abstract
Abstract A secure embedded memory management unit for a microprocessor is used for encrypted instruction and data transfer from an external memory. Physical security is obtained by embedding the direct memory access controller on the same chip with a microprocessor core, an internal memory, and an encryption/decryption logic. Data transfer to and from an external memory takes place between the external memory and the memory controller of the memory management unit. All firmware to and from the external memory is handled on a page-by-page basis. Since all of the processing takes place on buses internal to the chip, detection of clear unencrypted instructions and data is prevented.
Inventors
- 👤 Richard Takahashi
- 👤 Daniel N. Heer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:19
CPC Classifications
G; G06; G06F; G06F21/00; G06F21/70; G06F21/86; G06F21/78; G06F21/79; G06F2207/00; G06F2207/72; G06F2207/7219
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
195 words
A secure embedded memory management unit for encrypted data and instruction transfer from an external memory including in combination: a microprocessor core; an internal memory; an interface bus; a secure direct memory access controller internally coupled with and physically embedded with said microprocessor core and said internal memory in the same integrated circuit (IC) chip, said controller coupled with said interface bus for input/output (I/O) transfer of page blocks of encrypted data and instructions to and from an external memory; and encryption/decryption logic in said IC chip internally coupled with and physically embedded with said microprocessor core, said internal memory and said direct memory access controller and operating to encrypt data and instructions supplied thereto from said internal memory and transferring said encrypted data and instructions to said direct memory access controller for transfer from said controller and through said interface thereof to an external memory; and said encryption/decryption logic operating to decrypt data and instructions supplied to said interface of said direct memory access controller from said external memory and through said controller to said encryption/decryption logic for supplying said decrypted data and instructions to said internal memory for use by said microprocessor core.
Claim 2
Dependent Claim
195 words
A secure embedded memory management unit for encrypted data and instruction transfer from an external memory including in combination: a microprocessor core; an internal memory; an interface bus; a secure direct memory access controller internally coupled with and physically embedded with said microprocessor core and said internal memory in the same integrated circuit (IC) chip, said controller coupled with said interface bus for input/output (I/O) transfer of page blocks of encrypted data and instructions to and from an external memory; and encryption/decryption logic in said IC chip internally coupled with and physically embedded with said microprocessor core, said internal memory and said direct memory access controller and operating to encrypt data and instructions supplied thereto from said internal memory and transferring said encrypted data and instructions to said direct memory access controller for transfer from said controller and through said interface thereof to an external memory; and said encryption/decryption logic operating to decrypt data and instructions supplied to said interface of said direct memory access controller from said external memory and through said controller to said encryption/decryption logic for supplying said decrypted data and instructions to said internal memory for use by said microprocessor core.
Claim 3
Dependent Claim
14 words
The combination according to claim 1 wherein said internal memory is a read/write memory.
Claim 4
Dependent Claim
43 words
The combination according to claim 2 further including a key register on said chip coupled with said direct memory access controller and programmed for establishing the timing of said encryption of said data and instructions and said decryption of said data and instructions.
Claim 5
Dependent Claim
14 words
The combination according to claim 1 wherein said internal memory is an SRAM memory.
Claim 6
Dependent Claim
51 words
The combination according to claim 1 further including a key register on said chip coupled with said direct memory access controller and programmed at the time of manufacture of said chip for establishing the timing of said encryption of said data and instructions and said decryption of said data and instructions.
Claim 7
Independent Claim
133 words
A method for securely decrypting and encrypting information obtained from and supplied to an external memory comprising the steps of: fabricating a microprocessor core, an internal memory, and a secure direct memory controller on the same integrated circuit chip with internal coupling on said chip between said microprocessor core, said internal memory and said direct memory access controller; transferring encrypted data and instructions to and from an external memory through an interface between said direct memory access controller and said external memory; providing encryption/decryption logic in said integrated circuit chip, with internal buses in said chip interconnecting said direct memory access controller, said microprocessor core, said internal memory, and said encryption/decryption logic to permit decrypting data and instructions obtained from said external memory by said direct memory access controller entirely within said chip.
Claim 8
Independent Claim
133 words
A method for securely decrypting and encrypting information obtained from and supplied to an external memory comprising the steps of: fabricating a microprocessor core, an internal memory, and a secure direct memory controller on the same integrated circuit chip with internal coupling on said chip between said microprocessor core, said internal memory and said direct memory access controller; transferring encrypted data and instructions to and from an external memory through an interface between said direct memory access controller and said external memory; providing encryption/decryption logic in said integrated circuit chip, with internal buses in said chip interconnecting said direct memory access controller, said microprocessor core, said internal memory, and said encryption/decryption logic to permit decrypting data and instructions obtained from said external memory by said direct memory access controller entirely within said chip.
Claim 9
Dependent Claim
75 words
The method according to claim 6 further including the steps of supplying unencrypted data and instructions from said microprocessor core to said internal memory, transferring said data and instructions from said internal memory to said encryption/decryption logic for encrypting said data and instructions; supplying said encrypted data and instructions to said direct memory access controller, supplying said encrypted data and instructions from said direct memory access controller to an external memory connected with said interface.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-19 | 2002-04-20 | 2002-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-19 | 2006-04-20 | 2006-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-19 | 2010-04-20 | 2010-10-20 | $7700.00 | Window Closed / Lapsed |