US5825709A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Sharp Corp
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Filing: 1997-01-14
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Granted: 1998-10-20
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Expires: 2017-01-14
Abstract
Abstract A semiconductor memory device of this invention includes: a memory cell array including a plurality of bit blocks each including a plurality of bit line groups each including a plurality of bit lines; a row decoder for designating a row over the plurality of bit blocks based on a row address so that data stored in memory cells on the designated row is read out to bit lines corresponding to the memory cells; a column decoder for designating a plurality of the bit lines each belonging to different one of the bit line groups based on a column address; a plurality of sense amplifiers each provided for one of the plurality of bit line groups for sensing and amplifying data on the designated bit lines; a plurality of latch circuits each provided for one of the plurality of sense amplifiers for latching outputs of the plurality of sense amplifiers; and a selector for alternately selecting one of outputs of the plurality of latch circuits corresponding to different bit line groups, thereby rapidly outputting the data.
Inventors
- 👤 Masakazu Kobayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 00:18
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/10; G11C7/1015; G11C7/1042
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
228 words
A semiconductor memory device comprising: a memory cell array including a plurality of bit blocks each including a plurality of bit line groups each including a plurality of bit lines; a row decoder for designating a row over the plurality of bit blocks based on a row address so that data stored in memory cells on the designated row is read out to bit lines corresponding to the memory cells; a column decoder for alternately designating a plurality of the bit lines corresponding to the memory cells on the designated row, each belonging to a different one of the bit line groups for each of the bit blocks based on a column address while the row decoder maintains the designation of the row over the plurality of bit blocks based on the row address; a plurality of sense amplifiers each provided for one of the plurality of bit line groups for sensing and amplifying data on the designated bit lines; a plurality of latch circuits each provided for one of the plurality of sense amplifiers for latching outputs of the plurality of sense amplifiers; and a selector for alternately selecting one of outputs of the plurality of latch circuits corresponding to different bit line groups, thereby rapidly outputting the data; a controller for alternately operating one of the plurality of sense amplifiers corresponding to different bit line groups.
Claim 2
Dependent Claim
228 words
A semiconductor memory device comprising: a memory cell array including a plurality of bit blocks each including a plurality of bit line groups each including a plurality of bit lines; a row decoder for designating a row over the plurality of bit blocks based on a row address so that data stored in memory cells on the designated row is read out to bit lines corresponding to the memory cells; a column decoder for alternately designating a plurality of the bit lines corresponding to the memory cells on the designated row, each belonging to a different one of the bit line groups for each of the bit blocks based on a column address while the row decoder maintains the designation of the row over the plurality of bit blocks based on the row address; a plurality of sense amplifiers each provided for one of the plurality of bit line groups for sensing and amplifying data on the designated bit lines; a plurality of latch circuits each provided for one of the plurality of sense amplifiers for latching outputs of the plurality of sense amplifiers; and a selector for alternately selecting one of outputs of the plurality of latch circuits corresponding to different bit line groups, thereby rapidly outputting the data; a controller for alternately operating one of the plurality of sense amplifiers corresponding to different bit line groups.
Claim 3
Dependent Claim
50 words
A semiconductor memory device according to claim 1, wherein while the sense amplifiers sense the data on the bit line designated by the column decoder, the bit lines belonging to the bit line group which is not the bit line group to which the designated bit line belongs are precharged.
Claim 4
Dependent Claim
50 words
A semiconductor memory device according to claim 1, wherein while the sense amplifiers sense the data on the bit line designated by the column decoder, the bit lines belonging to the bit line group which is not the bit line group to which the designated bit line belongs are precharged.
Claim 5
Dependent Claim
27 words
A semiconductor memory device according to claim 1, wherein the plurality of bit line groups include an even-numbered bit line group and an odd-numbered bit line group.
Claim 6
Dependent Claim
352 words
A semiconductor memory device comprising: a memory cell array including a plurality of bit blocks each including a plurality of bit line groups each including a plurality of bit lines; a row decoder for designating a row over the plurality of bit blocks based on a row address so that data stored in memory cells on the designated row is read out to bit lines corresponding to the memory cells; a column decoder for alternately designating a plurality of the bit lines each belonging to different one of the bit line groups for each of the bit blocks based on a column address while the row decoder maintains the designation of the row over the plurality of bit blocks based on the row address; a plurality of sense amplifiers each provided for one of the plurality of bit line groups for sensing and amplifying data on the designated bit lines; a plurality of latch circuits each provided for one of the plurality of sense amplifiers for latching outputs of the plurality of sense amplifiers; and a selector for alternately selecting one of outputs of the plurality of latch circuits corresponding to different bit line groups, thereby rapidly outputting the data; wherein the plurality of bit line groups include an even-numbered bit line group and an odd-numbered bit line group; the plurality of sense amplifiers include a plurality of first sense amplifiers each provided for the odd-numbered bit line groups for sensing and amplifying data on the designated bit lines, and a plurality of second sense amplifiers each provided for the even-numbered bit line groups for sensing and amplifying data on the designated bit lines; the first sense amplifiers sensing the data on the bit lines belonging to the odd-numbered bit line group, while the second sense amplifiers do not sense the data on the bit lines belonging to the even-numbered bit line group; the second sense amplifiers sensing the data on the bit lines belonging to the even-numbered bit line group, while the first sense amplifiers do not sense the data on the bit lines belonging to the odd-numbered bit line group.
Claim 7
Dependent Claim
352 words
A semiconductor memory device comprising: a memory cell array including a plurality of bit blocks each including a plurality of bit line groups each including a plurality of bit lines; a row decoder for designating a row over the plurality of bit blocks based on a row address so that data stored in memory cells on the designated row is read out to bit lines corresponding to the memory cells; a column decoder for alternately designating a plurality of the bit lines each belonging to different one of the bit line groups for each of the bit blocks based on a column address while the row decoder maintains the designation of the row over the plurality of bit blocks based on the row address; a plurality of sense amplifiers each provided for one of the plurality of bit line groups for sensing and amplifying data on the designated bit lines; a plurality of latch circuits each provided for one of the plurality of sense amplifiers for latching outputs of the plurality of sense amplifiers; and a selector for alternately selecting one of outputs of the plurality of latch circuits corresponding to different bit line groups, thereby rapidly outputting the data; wherein the plurality of bit line groups include an even-numbered bit line group and an odd-numbered bit line group; the plurality of sense amplifiers include a plurality of first sense amplifiers each provided for the odd-numbered bit line groups for sensing and amplifying data on the designated bit lines, and a plurality of second sense amplifiers each provided for the even-numbered bit line groups for sensing and amplifying data on the designated bit lines; the first sense amplifiers sensing the data on the bit lines belonging to the odd-numbered bit line group, while the second sense amplifiers do not sense the data on the bit lines belonging to the even-numbered bit line group; the second sense amplifiers sensing the data on the bit lines belonging to the even-numbered bit line group, while the first sense amplifiers do not sense the data on the bit lines belonging to the odd-numbered bit line group.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-19 | 2002-04-20 | 2002-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-19 | 2006-04-20 | 2006-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-19 | 2010-04-20 | 2010-10-20 | $7700.00 | Window Closed / Lapsed |