US5519655A
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Memory architecture using new power saving row decode implementation
Assignee: Texas Instruments Inc
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Filing: 1994-09-29
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Granted: 1996-05-21
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Expires: 2014-09-29
Abstract
Abstract The invention disclosed herein comprises a memory architecture using a new power saving ROW decode implementation. The new power saving ROW decode implementation uses a built in column mux of two. Two ROW drivers are provided for each ROW address. Each row signal from an individual ROW driver connects to every other memory cell (10). An individual ROW driver is selected based on the select signals used in the column mux. Being that the ROW drivers are muxed along with the columns, only memory cells of interest are selected. All unselected memory cell bit lines remain precharged from the previous precharge cycle thus reducing precharge power consumption as compared with previous memory architectures.
Inventors
- 👤 Craig B. Greenberg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 02:31
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/16; G11C7/00; G11C7/12; G11C8/10
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
91 words
A device, comprising: rows and columns of memory cells; column multiplex circuits each coupling two columns of memory cells to a respective sense amplifier; two ROW drivers provided for each ROW address; and a first ROW signal line coupling one of said two ROW drivers to a first group of every other memory cell in a respective row of memory cells and a second ROW signal line coupling the other of said two ROW drivers to a second group of every other memory cell in said respective row of memory cells.
Claim 2
Independent Claim
91 words
A device, comprising: rows and columns of memory cells; column multiplex circuits each coupling two columns of memory cells to a respective sense amplifier; two ROW drivers provided for each ROW address; and a first ROW signal line coupling one of said two ROW drivers to a first group of every other memory cell in a respective row of memory cells and a second ROW signal line coupling the other of said two ROW drivers to a second group of every other memory cell in said respective row of memory cells.
Claim 3
Dependent Claim
17 words
The device of claim 1 in which said device is a single port random access memory (RAM).
Claim 4
Dependent Claim
16 words
The device of claim 1 in which said column multiplex circuits have a ratio of 2:1.
Claim 5
Dependent Claim
14 words
The device of claim 1 in which each ROW address addresses two ROW drivers.
Claim 6
Dependent Claim
24 words
The device of claim 4 in which an individual ROW driver is selected based on the select signals used in the column multiplex circuits.
Claim 7
Independent Claim
104 words
A device, comprising: rows and columns of memory cells; column multiplex circuits each coupling two columns of memory cells to a respective sense amplifier; two ROW drivers provided for each ROW address: a first ROW signal line coupling one of said two ROW drivers to a first group of every other memory cell in a respective row of memory cells and a second ROW signal line coupling the other of said two ROW drivers to a second group of every, other memory cell in said respective row of memory cells; and decoding logic for coupling ROW and column address lines to said ROW drivers.
Claim 8
Independent Claim
104 words
A device, comprising: rows and columns of memory cells; column multiplex circuits each coupling two columns of memory cells to a respective sense amplifier; two ROW drivers provided for each ROW address: a first ROW signal line coupling one of said two ROW drivers to a first group of every other memory cell in a respective row of memory cells and a second ROW signal line coupling the other of said two ROW drivers to a second group of every, other memory cell in said respective row of memory cells; and decoding logic for coupling ROW and column address lines to said ROW drivers.
Claim 9
Dependent Claim
46 words
The device of claim 6 in which said decoding logic comprises a NAND gate having a first input connected to one ROW select signal line, a second input connected to another ROW select signal line and a third input connected to a column select signal line.
Claim 10
Independent Claim
194 words
A device, comprising: rows and columns of dual port memory cells; a first column multiplex circuit coupled to memory cells in a column of said dual port memory cells, each memory cell being connected to one of said dual ports; a second column multiplex circuit coupled to memory cells in said column of dual port memory cells, each memory cell being connected to the other of said dual ports; four ROW drivers provided for each ROW address; and a first ROW signal line coupling one of said four ROW drivers to a first group of every other memory cells in a respective row of memory cells, a second ROW signal line coupling a second of said four ROW drivers to a second group of every other memory cells in said respective row of memory cells, a third ROW signal line coupling a third of said four ROW drivers to said first group of every other memory cells in said respective row of memory cells and a fourth ROW signal line coupling a fourth of said four ROW drivers to said second group of every other memory cells in said respective row of memory cells.
Claim 11
Independent Claim
194 words
A device, comprising: rows and columns of dual port memory cells; a first column multiplex circuit coupled to memory cells in a column of said dual port memory cells, each memory cell being connected to one of said dual ports; a second column multiplex circuit coupled to memory cells in said column of dual port memory cells, each memory cell being connected to the other of said dual ports; four ROW drivers provided for each ROW address; and a first ROW signal line coupling one of said four ROW drivers to a first group of every other memory cells in a respective row of memory cells, a second ROW signal line coupling a second of said four ROW drivers to a second group of every other memory cells in said respective row of memory cells, a third ROW signal line coupling a third of said four ROW drivers to said first group of every other memory cells in said respective row of memory cells and a fourth ROW signal line coupling a fourth of said four ROW drivers to said second group of every other memory cells in said respective row of memory cells.
Claim 12
Dependent Claim
17 words
The device of claim 8 in which said device is a dual port random access memory (RAM).
Claim 13
Dependent Claim
16 words
The device of claim 8 in which said column multiplex circuits have a ratio of 2:1.
Claim 14
Dependent Claim
17 words
The device of claim 8 in which each ROW address of each port addresses two ROW drivers.
Claim 15
Dependent Claim
29 words
The device of claim 11 in which an individual ROW driver of a port is selected based on the select signals used in the column mux of said port.
Claim 16
Independent Claim
201 words
A device, comprising: rows and columns of dual port memory cells; a first column multiplex circuit coupled to memory cells in a column of said dual port memory cells, each memory cell being connected to one of said dual ports; a second column multiplex circuit coupled to memory cells in said column of dual port memory cells, each memory, cell being connected to the other of said dual ports; four ROW drivers provided for each ROW address; a first ROW signal line coupling one of said four ROW drivers to a first group of every, other memory cells in a respective row of memory cells, a second ROW signal line ROW drivers to said first group of every other memory cells in said respective row of coupling a second of said four ROW drivers to a second in said respective row of memory cells, a third ROW signal line coupling a third of said four memory cells and a fourth ROW signal line coupling a fourth of said four ROW drivers to said second group of every other memory cells in said respective row of memory cells; and decoding logic for coupling ROW and column address lines to said ROW drivers.
Claim 17
Independent Claim
201 words
A device, comprising: rows and columns of dual port memory cells; a first column multiplex circuit coupled to memory cells in a column of said dual port memory cells, each memory cell being connected to one of said dual ports; a second column multiplex circuit coupled to memory cells in said column of dual port memory cells, each memory, cell being connected to the other of said dual ports; four ROW drivers provided for each ROW address; a first ROW signal line coupling one of said four ROW drivers to a first group of every, other memory cells in a respective row of memory cells, a second ROW signal line ROW drivers to said first group of every other memory cells in said respective row of coupling a second of said four ROW drivers to a second in said respective row of memory cells, a third ROW signal line coupling a third of said four memory cells and a fourth ROW signal line coupling a fourth of said four ROW drivers to said second group of every other memory cells in said respective row of memory cells; and decoding logic for coupling ROW and column address lines to said ROW drivers.
Claim 18
Dependent Claim
18 words
The device of claim 8 further including sense amplifiers coupled to said first and second column multiplex circuits.
Claim 19
Independent Claim
89 words
A device, comprising: rows and columns of memory cells; column multiplex circuits each coupling at least two columns of memory cells to a respective sense amplifier; at least two ROW drivers provided for each ROW address; and a first ROW signal line coupling one of said ROW drivers to a first group of memory cells in a respective row of memory cells and a second ROW signal line coupling another one of said ROW drivers to a second group of memory cells in said respective row of memory cells.
Claim 20
Independent Claim
89 words
A device, comprising: rows and columns of memory cells; column multiplex circuits each coupling at least two columns of memory cells to a respective sense amplifier; at least two ROW drivers provided for each ROW address; and a first ROW signal line coupling one of said ROW drivers to a first group of memory cells in a respective row of memory cells and a second ROW signal line coupling another one of said ROW drivers to a second group of memory cells in said respective row of memory cells.
Claim 21
Dependent Claim
17 words
The device of claim 15 in which said device is a single port random access memory (RAM).
Claim 22
Dependent Claim
24 words
The device of claim 15 in which an individual ROW driver is selected based on the select signals used in the column multiplex circuits.
Claim 23
Independent Claim
101 words
A device, comprising: rows and columns of memory cells; column multiplex circuits each coupling at least two columns of memory cells to..a respective sense amplifier; at least two ROW drivers provided for each ROW address; a first ROW signal line coupling one of said ROW drivers to a first group of memory cells in a respective row of memory cells and a second ROW signal line coupling another one of said ROW drivers to a second group of memory cells in said respective row of memory cells; and decoding logic for coupling ROW and column address lines to said ROW drivers.
Claim 24
Independent Claim
101 words
A device, comprising: rows and columns of memory cells; column multiplex circuits each coupling at least two columns of memory cells to..a respective sense amplifier; at least two ROW drivers provided for each ROW address; a first ROW signal line coupling one of said ROW drivers to a first group of memory cells in a respective row of memory cells and a second ROW signal line coupling another one of said ROW drivers to a second group of memory cells in said respective row of memory cells; and decoding logic for coupling ROW and column address lines to said ROW drivers.
Claim 25
Dependent Claim
14 words
The device of claim 1 in which each memory cell has a common I/O.
Claim 26
Dependent Claim
14 words
The device of claim 8 in which each memory cell has a common I/O.
Claim 27
Dependent Claim
14 words
The device of claim 15 in which each memory cell has a common I/O.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-21 | 1999-11-20 | 2000-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-21 | 2003-11-20 | 2004-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-21 | 2007-11-20 | 2008-05-21 | $7700.00 | Window Closed / Lapsed |