Non-volatile programmable read only memory device having write-in unit sequentially writing data bits into memory cells for programming

Claim 2

A non-volatile programmable read only memory device comprising: a) a plurality of memory cells arranged in rows and columns and divided into a plurality of memory cell blocks each including columns of said memory cells; b) a plurality of word lines coupled to said rows of said memory cells and driven for selecting one of said rows of said memory cells; c) a plurality of column selectors respectively associated with said memory cell blocks, each of said column selectors being responsive to a column selecting signal for selecting a column of said memory cells from said associated memory cell block; d) a plurality of data latching circuits for storing a plurality of write-in data bits, respectively; e) a plurality of write-in circuits respectively coupled to said plurality of data latching circuits and respectively generating a plurality of write-in signals each being indicative of a respective one of said respective write-in data bits, said plurality of write-in signals being supplied to said column selectors, respectively; f) a write-in controlling unit responsive to an external controlling signal and sequentially producing a plurality of write-in controlling signals, wherein a time delay is introduced between said plurality of write-in controlling signals; and g) a transfer gate array coupled between said plurality of write-in circuits and said plurality of column selectors, said transfer gate array having a plurality of transfer transistors divided into a plurality of transfer gate groups, said transfer gate groups being respectively response to said plurality of write-in controlling signals for sequentially transferring said write-in signals to said plurality of column selectors.

Claim 3

The non-volatile programmable read only memory device as set forth in claim 1 wherein said write-in circuits are coupled between said latching circuits and said transfer gate array, said transfer gate array propagating said write-in signals.

Claim 4

The non-volatile programmable read only memory device as set forth in claim 2 wherein said write-in controlling signals are partially overlapped with each other.

Claim 5

The non-volatile programmable read only memory device as set forth in claim 3 in which said non-volatile programmable read only memory device further comprises a shifting unit coupled between said transfer gate array and said column selectors, said shifting unit being operative to propagate said write-in signals to said column selectors, respectively, in a programming mode, said shifting unit being further operative to transfer data bits from one of said column selectors to a sense amplifier circuit.

Claim 6

A non-volatile programmable read only memory device comprising: a) a plurality of memory cells arranged to tows and columns and divided into a plurality of memory cell blocks each including columns of said memory cells; b) a plurality of word lines coupled to said rows of said memory cells and driven for selecting one of said rows of said memory cells; c) a plurality of column selectors respectively associated with said memory cell blocks, each of said column selectors being responsive to a column selecting signal for selecting a column of said memory cells from said associated memory cell block; d) a plurality of data latching circuits for storing a plurality of write-in data bits, respectively; e) a plurality of write-in circuits associated with said plurality of data latching circuits and respectively generating a plurality of write-in signals each being indicative of a respective one of said respective write-in data bits, said plurality of write-in signals being supplied to said column selectors, respectively, the plurality of write-in circuits for respectively writing the plurality of write-in data bits into the non-volatile programmable read only memory device; f) a write-in controlling unit responsive to an external controlling signal and sequentially producing a plurality of write-in controlling signals, wherein a time delay is introduced between said plurality of write-in controlling signals; and g) a transfer gate array having a plurality of transfer transistors divided into a plurality of transfer gate groups, said transfer gate groups being respectively responsive to said plurality of write-in controlling signals for sequentially transferring said write-in data bits to said plurality of write-in circuits.

Claim 7

A non-volatile programmable read only memory device comprising: a) a plurality of memory cells arranged to tows and columns and divided into a plurality of memory cell blocks each including columns of said memory cells; b) a plurality of word lines coupled to said rows of said memory cells and driven for selecting one of said rows of said memory cells; c) a plurality of column selectors respectively associated with said memory cell blocks, each of said column selectors being responsive to a column selecting signal for selecting a column of said memory cells from said associated memory cell block; d) a plurality of data latching circuits for storing a plurality of write-in data bits, respectively; e) a plurality of write-in circuits associated with said plurality of data latching circuits and respectively generating a plurality of write-in signals each being indicative of a respective one of said respective write-in data bits, said plurality of write-in signals being supplied to said column selectors, respectively, the plurality of write-in circuits for respectively writing the plurality of write-in data bits into the non-volatile programmable read only memory device; f) a write-in controlling unit responsive to an external controlling signal and sequentially producing a plurality of write-in controlling signals, wherein a time delay is introduced between said plurality of write-in controlling signals; and g) a transfer gate array having a plurality of transfer transistors divided into a plurality of transfer gate groups, said transfer gate groups being respectively responsive to said plurality of write-in controlling signals for sequentially transferring said write-in data bits to said plurality of write-in circuits.

Claim 8

The non-volatile programmable read only memory device as set forth in claim 5 in which said transfer gate array is coupled between said latching circuits and said write-in circuits for selectively propagating said write-in data bits, said latching circuits being divided into a plurality of latching circuit groups respectively connectable through said plurality of transfer gate groups to said write-in circuits, each of said write-in circuits having a plurality of output nodes so as to sequentially supply said write-in signals indicative of said write-in data bits sequentially fed from said associated latching circuits.

Claim 9

The non-volatile programmable read only memory device as set forth in claim 6 wherein the plurality of write-in controlling signals include first and second write-in controlling signals, and wherein said second write-in controlling signal is enabled immediately after said first write-in controlling signal is disabled.

Claim 10

The non-volatile programmable read only memory device as set forth in claim 6, in which said non-volatile programmable read only memory device further comprises a shifting unit coupled between said write-in circuits and said column selectors, said shifting unit being operative to propagate said write-in signals to said column selectors, respectively, in a programmable mode, said shifting unit being further operative to transfer data bits read out from one of said column selectors to a sense amplifier circuit.