Transformer circuit, double-balanced mixer

Claim 2

Transformer circuit for converting an asymmetrical input signal into a pair of substantially symmetrical output signal currents, comprising a first and a second transistor, the emitter of the first transistor being coupled to an asymmetrical input terminal, the collector of the first transistor and the collector of the second transistor being coupled to a first and to a second symmetrical output terminal, respectively, wherein the asymmetrical input terminal is coupled to a node commonly coupled to the emitter of the first transistor and to the base of the second transistor, said node being connected to a point of reference voltage via a bidirectional current path, and wherein the first and the second transistor are connected in common base configuration and in common emitter configuration, respectively.

Claim 3

The transformer circuit according to claim 1, wherein a cascode transistor in common base configuration is coupled between the collector of the second transistor and the second symmetrical output terminal.

Claim 4

The transformer circuit according to claim 1 further comprising an input transistor coupled between the asymmetrical input terminal and the node and having a control electrode coupled to a reference voltage.

Claim 5

The transformer circuit according to claim 1, wherein said bidirectional current path includes a DC-blocking capacitor coupled between the node and the base of the second transistor.

Claim 6

Transformer circuit according to claim 1, which further comprises a bias control loop comprising a first current sensing circuit coupled to the first transistor, a second current sensing circuit coupled to the second transistor, a difference detection circuit having a first and a second input coupled to respective outputs of the first and the second current sensing circuit, the output of the difference detection circuit being coupled to the base of the first transistor via at least one loop capacitor.

Claim 7

Transformer circuit according to claim 5, wherein a loop transistor is coupled between the output of the difference detection circuit and the base of the first transistor, a base-emitter junction of the loop transistor constituting said loop capacitor.

Claim 8

Transformer circuit according to claim 2, wherein a first impedance is coupled between the emitter of the first transistor and the node and a second impedance is coupled between the emitter of the second transistor and signal ground.

Claim 9

The transformer circuit according to claim 2, wherein said bidirectional current path includes a DC blocking capacitor coupled between the node and the base of the second transistor.

Claim 10

The transformer circuit according to claim 1 wherein a first impedance is coupled between the emitter of the first transistor and said node and a second impedance is coupled between the emitter of the second transistor and signal ground.

Claim 11

The transformer circuit according to claim 1 further comprising circuit means coupled to said first and second transistors so as to maintain bias currents of said transistors substantially equal.

Claim 12

A double-balanced mixer circuit comprising: a first differential pair of first and second mixer transistors, whose emitters are coupled to a first common emitter terminal, a second differential pair of third and fourth mixer transistors, whose emitters are coupled to a second common emitter terminal, bases of the first and the fourth transistor and bases of the second and the third transistor being coupled to a first common and a second common base terminal respectively, for receiving a mixing signal, wherein an asymmetrical input terminal is coupled to a node coupled to the first common emitter terminal and to the base of a transistor connected in a common emitter configuration and having its collector coupled to the second common emitter terminal, wherein said node is coupled to the first common emitter terminal via a further transistor connected in common base configuration with its emitter coupled to the node and its collector coupled to the first common emitter terminal and said node is connected to a point of reference voltage via circuit means that provide an impedance between the node and point of reference voltage which is at least an order or magnitude higher than the input impedance of the emitter of the further transistor whereby a signal current received at the asymmetrical input terminal flows substantially and continuously to the first common emitter terminal via the emitter of said further transistor.

Claim 13

A double-balanced mixer circuit comprising: a first differential pair of first and second mixer transistors, whose emitters are coupled to a first common emitter terminal, a second differential pair of third and fourth mixer transistors, whose emitters are coupled to a second common emitter terminal, bases of the first and the fourth transistor and bases of the second and the third transistor being coupled to a first common and a second common base terminal respectively, for receiving a mixing signal, wherein an asymmetrical input terminal is coupled to a node coupled to the first common emitter terminal and to the base of a transistor connected in a common emitter configuration and having its collector coupled to the second common emitter terminal, wherein said node is coupled to the first common emitter terminal via a further transistor connected in common base configuration with its emitter coupled to the node and its collector coupled to the first common emitter terminal and said node is connected to a point of reference voltage via circuit means that provide an impedance between the node and point of reference voltage which is at least an order or magnitude higher than the input impedance of the emitter of the further transistor whereby a signal current received at the asymmetrical input terminal flows substantially and continuously to the first common emitter terminal via the emitter of said further transistor.

Claim 14

The double-balanced mixer circuit according to claim 11 wherein said node is coupled to the base of said transistor via a capacitor.

Claim 15

A transformer circuit comprising: an asymmetrical input terminal, a first and a second symmetrical output terminal at which is derived a pair of symmetrical output signals, a first transistor in common base configuration whose collector is coupled to said first symmetrical output terminal, a second transistor in common emitter configuration whose collector is coupled to said second symmetrical output terminal, a node commonly coupled to the emitter of the first transistor, to the base of the second transistor, to said asymmetrical input terminal and to signal ground via circuit means providing an impedance between the node and signal ground which is at least an order of magnitude higher than an input impedance formed by the emitter of the first transistor, the circuit means being coupled so as to direct a signal current received at said asymmetrical input terminal to substantially flow to the first symmetrical output terminal via the emitter of said first transistor.

Claim 16

A transformer circuit comprising: an asymmetrical input terminal, a first and a second symmetrical output terminal at which is derived a pair of symmetrical output signals, a first transistor in common base configuration whose collector is coupled to said first symmetrical output terminal, a second transistor in common emitter configuration whose collector is coupled to said second symmetrical output terminal, a node commonly coupled to the emitter of the first transistor, to the base of the second transistor, to said asymmetrical input terminal and to signal ground via circuit means providing an impedance between the node and signal ground which is at least an order of magnitude higher than an input impedance formed by the emitter of the first transistor, the circuit means being coupled so as to direct a signal current received at said asymmetrical input terminal to substantially flow to the first symmetrical output terminal via the emitter of said first transistor.

Claim 17

A transformer circuit according to claim 13 wherein the circuit means further comprises a third transistor having a collector which is coupled to the emitter of the first transistor via a first impedance and which collector is coupled to the base of the second transistor, said asymmetrical input terminal being coupled to the emitter of said third transistor, and means coupling the base of said third transistor to a reference voltage terminal.

Claim 18

The transformer circuit according to claim 13, further comprising a DC blocking capacitor coupled between said node and the base of the second transistor.

Claim 19

The transformer circuit according to claim 13, wherein the circuit means further comprises a bias control loop having: current sensing means for providing a scaled replica of the collector current of the first transistor and that of the collector current of the second transistor, respectively; difference detection means for providing a difference current proportional to the difference between the scaled replica currents; and feedback means for supplying said difference current to the base of the first transistor.

Claim 20

The transformer circuit according to claim 13 wherein a first impedance is coupled between the emitter of the first transistor and said node and a second impedance is coupled between the emitter of the second transistor and signal ground.

Claim 21

The transformer circuit according to claim 17 wherein said circuit means includes an input transistor which is coupled between the asymmetrical input terminal and said node, said input transistor having a control electrode coupled to signal ground.

Claim 22

The transformer circuit according to claim 13, wherein a cascode transistor in common base configuration is coupled between the collector of the second transistor and the second symmetrical output terminal.

Claim 23

The transformer circuit according to claim 16, wherein said feedback means comprise a loop transistor having a base-emitter junction that constitutes a loop capacitor.

Claim 24

A double-balanced mixer circuit comprising: a first differential pair of first and second mixer transistors, whose emitters are coupled to a common first emitter terminal, a second differential pair of third and fourth mixer transistors, whose emitters are coupled to a common second emitter terminal, bases of the first and the fourth transistor and bases of the second and the third transistor being coupled to a common first and a common second base terminal, respectively, which in operation receive a mixing signal, wherein the first common emitter terminal and the second common emitter terminal are coupled to the first symmetrical output terminal and the second symmetrical output terminal, respectively, of the transformer circuit according to claim 13.

Claim 25

A double-balanced mixer circuit comprising: a first differential pair of first and second mixer transistors, whose emitters are coupled to a first common emitter terminal, a second differential pair of third and fourth mixer transistors, whose emitters are coupled to a second common emitter terminal, bases of the first and the fourth transistor and bases of the second and the third transistor being coupled to a first common and a second common base terminal respectively, for receiving a mixing signal, wherein an asymmetrical input terminal is coupled to a node coupled to the first common emitter terminal and to the base of a transistor connected in a common emitter configuration and having its collector coupled to the second common emitter terminal, wherein said node is coupled to the first common emitter terminal via a further transistor connected in common base configuration with its emitter coupled to the node and its collector coupled to the first common emitter terminal, and further comprising an input transistor coupled between the asymmetrical input terminal and the node and having a control electrode coupled to a reference voltage.

Claim 26

A double-balanced mixer circuit comprising: a first differential pair of first and second mixer transistors, whose emitters are coupled to a first common emitter terminal, a second differential pair of third and fourth mixer transistors, whose emitters are coupled to a second common emitter terminal, bases of the first and the fourth transistor and bases of the second and the third transistor being coupled to a first common and a second common base terminal respectively, for receiving a mixing signal, wherein an asymmetrical input terminal is coupled to a node coupled to the first common emitter terminal and to the base of a transistor connected in a common emitter configuration and having its collector coupled to the second common emitter terminal, wherein said node is coupled to the first common emitter terminal via a further transistor connected in common base configuration with its emitter coupled to the node and its collector coupled to the first common emitter terminal, and further comprising an input transistor coupled between the asymmetrical input terminal and the node and having a control electrode coupled to a reference voltage.

Claim 27

A double-balanced mixer circuit comprising: a first differential pair of first and second mixer transistors, whose emitters are coupled to a first common emitter terminal, a second differential pair of third and fourth mixer transistors, whose emitters are coupled to a second common emitter terminal, bases of the first and the fourth transistor and bases of the second and the third transistor being coupled to a first common and a second common base terminal respectively, for receiving a mixing signal, wherein an asymmetrical input terminal is coupled to a node coupled to the first common emitter terminal and to the base of a transistor connected in a common emitter configuration and having its collector coupled to the second common emitter terminal, wherein said node is coupled to the first common emitter terminal via a further transistor connected in common base configuration with its emitter coupled to the node and its collector coupled to the first common emitter terminal, and further comprising a cascode transistor in common base configuration coupled between the collector of said transistor and the second common emitter terminal.

Claim 28

A double-balanced mixer circuit comprising: a first differential pair of first and second mixer transistors, whose emitters are coupled to a first common emitter terminal, a second differential pair of third and fourth mixer transistors, whose emitters are coupled to a second common emitter terminal, bases of the first and the fourth transistor and bases of the second and the third transistor being coupled to a first common and a second common base terminal respectively, for receiving a mixing signal, wherein an asymmetrical input terminal is coupled to a node coupled to the first common emitter terminal and to the base of a transistor connected in a common emitter configuration and having its collector coupled to the second common emitter terminal, wherein said node is coupled to the first common emitter terminal via a further transistor connected in common base configuration with its emitter coupled to the node and its collector coupled to the first common emitter terminal, and further comprising a cascode transistor in common base configuration coupled between the collector of said transistor and the second common emitter terminal.