US4216431A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit for frequency conversion
Assignee: Hitachi Ltd
•
Filing: 1978-09-07
•
Granted: 1980-08-05
•
Expires: 1998-09-07
Abstract
Abstract A frequency converter circuit suitable for being constructed in the form of an integrated circuit and adapted to the frequency conversion of a carrier chrominance signal for recording and reproducing chrominance video signals basically comprises a full balance type differential amplifier including three sets of paired differential transistors. Two sets of paired differential transistors, in which the collector of one transistor of one paired differential transistors is connected to that of the corresponding one transistor of the other paired differential transistors and the collector of the other transistor of the one paired differential transistors is connected to that of the other transistor of the other paired differential transistors, are provided for the output stage and have those collectors each connected to the respective emitters of grounded base transistors. The grounded base transistors have their collectors each connected to a load resistor. The output signal is picked up from the collector of one of the grounded base transistors.
Inventors
- 👤 Akira Shibata
- 👤 Yoshizumi Watatani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:31
CPC Classifications
H; H03; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/3036; H03G3/3042; H03C; H03C1/00; H03C1/52; H03C1/54; H03C1/542; H03C1/545; H03D; H03D7/00; H03D7/14; H03D7/1425; H03D7/1433; H03D2200/00; H03D2200/0041; H03D2200/0043; H03D2200/009
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
278 words
A frequency converter circuit for receiving a carrier signal and a signal to be frequency-converted and delivering out the frequency-converted signal with a minimized leakage of the carrier, comprising: a first transistor of grounded emitter connection as a constant current source; second and third transistors with their emitters each connected to the collector of said first transistor through a resistor; fourth and fifth transistors with their emitters connected in common and connected to the collector of said second transistor; sixth and seventh transistors with their emitters connected in common and connected to the collector of said third transistor; means for connecting the collectors of said fourth and sixth transistors to each other; means for connecting the collectors of said fifth and seventh transistors to each other; means for connecting the bases of said fourth and seventh transistors to each other; means for connecting the bases of said fifth and sixth transistors to each other; an eighth transistor with its emitter connected to the collectors of said fifth and seventh transistors connected in common; a load connected to the collector of said eighth transistor; a first signal applying terminal connected to one of the bases of said second and third transistors; a second signal applying terminal connected either to the bases of said fourth and seventh transistors connected in common or to the bases of said fifth and sixth transistors connected to each other; means for applying said signal to be frequency-converted to one of said first and second signal applying terminals and said carrier signal to the other of the said and second signal applying terminals; and an output terminal connected to the collector of said eighth transistor.
Claim 2
Dependent Claim
278 words
A frequency converter circuit for receiving a carrier signal and a signal to be frequency-converted and delivering out the frequency-converted signal with a minimized leakage of the carrier, comprising: a first transistor of grounded emitter connection as a constant current source; second and third transistors with their emitters each connected to the collector of said first transistor through a resistor; fourth and fifth transistors with their emitters connected in common and connected to the collector of said second transistor; sixth and seventh transistors with their emitters connected in common and connected to the collector of said third transistor; means for connecting the collectors of said fourth and sixth transistors to each other; means for connecting the collectors of said fifth and seventh transistors to each other; means for connecting the bases of said fourth and seventh transistors to each other; means for connecting the bases of said fifth and sixth transistors to each other; an eighth transistor with its emitter connected to the collectors of said fifth and seventh transistors connected in common; a load connected to the collector of said eighth transistor; a first signal applying terminal connected to one of the bases of said second and third transistors; a second signal applying terminal connected either to the bases of said fourth and seventh transistors connected in common or to the bases of said fifth and sixth transistors connected to each other; means for applying said signal to be frequency-converted to one of said first and second signal applying terminals and said carrier signal to the other of the said and second signal applying terminals; and an output terminal connected to the collector of said eighth transistor.
Claim 3
Dependent Claim
29 words
A frequency converter circuit according to claim 1, further comprising means for connecting a power supply to the collectors of said fourth and sixth transistors connected to each other.
Claim 4
Dependent Claim
41 words
A frequency converter circuit according to claim 1, further comprising a ninth transistor with its emitter connected to the bases of said fourth and sixth transistors connected to each other, and a load connected to the collector of said ninth transistor.
Claim 5
Dependent Claim
31 words
A frequency converter circuit according to claim 1, 2 or 3, wherein the base of said eighth transistor is connected to bias means having a low impedance against an AC signal.
Claim 6
Dependent Claim
38 words
A frequency converter circuit according to claim 3, wherein the base of said ninth transistor is connected to the base of said eighth transistor to be connected to bias means having a low impedance against an AC signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-08-05 | 1984-02-04 | 1984-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-08-05 | 1988-02-04 | 1988-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-08-05 | 1992-02-04 | 1992-08-05 | $7700.00 | Window Closed / Lapsed |