US3875522A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated direct-coupled electronic attenuator
Assignee: Signetics Corp
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Filing: 1973-04-13
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Granted: 1975-04-01
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Expires: 1993-04-13
Abstract
Abstract An integrated direct coupled electronic attenuator circuit provides both attenuation and switching between attenuation limits of 0 and 100 percent. Zero dc offset voltage is provided with the use of a pair of differential amplifiers driven by a common current source. Switching means are provided for controlling the partitioning of such current between the differential amplifier. Loads are coupled to the other side of the differential amplifiers to receive the current from the constant current source.
Inventors
- 👤 Werner H Hoefi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 02:57
CPC Classifications
H; H03; H03G; H03G1/00; H03G1/0005; H03G1/0088; H03G1/0017; H03G1/0023; H03H; H03H11/00; H03H11/02; H03H11/24
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
138 words
An integrated direct coupled electronic attenuator circuit comprising: first and second differential amplifiers each including a pair of transistors and each transistor having an input control terminal and first and second output terminals, said first output terminals of each pair of transistors being tied together at least one of said input control terminals receiving an ac input signal; a common constant current source, first and second switching means for coupling said constant current source to said tied pairs of said first output terminals, said switching means including means for selectively controlling the partitioning of said constant current between said first and second differential amplifiers; and load means coupled to the second output terminals of said differential amplifiers for concurrently receiving current from said constant current source which has been conducted through both said first and second differential amplifiers.
Claim 2
Dependent Claim
138 words
An integrated direct coupled electronic attenuator circuit comprising: first and second differential amplifiers each including a pair of transistors and each transistor having an input control terminal and first and second output terminals, said first output terminals of each pair of transistors being tied together at least one of said input control terminals receiving an ac input signal; a common constant current source, first and second switching means for coupling said constant current source to said tied pairs of said first output terminals, said switching means including means for selectively controlling the partitioning of said constant current between said first and second differential amplifiers; and load means coupled to the second output terminals of said differential amplifiers for concurrently receiving current from said constant current source which has been conducted through both said first and second differential amplifiers.
Claim 3
Dependent Claim
56 words
A circuit as in claim 1 where said load means include first and second transistors coupled together, such first transistor being connected to the second output terminals of both of said first transistors of said differential amplifiers and such second transistor being connected to the second output terminals of said second transistors of said differential amplifiers.
Claim 4
Dependent Claim
28 words
A circuit as in claim 2 where said load means includes a third transistor connected to said first transistor of said load means in a current multiplier configuration.
Claim 5
Dependent Claim
82 words
A circuit as in claim 1 where said load means includes a first pair of transistors coupling said first differential amplifier pair of transistors to a dc potential source, a second pair of transistors coupling said second differential amplifier pair of transistors to said dc potential source, and a third pair of transistors connected to ground through an output load resistor and to said dc potential source, all of the base inputs of said three pairs of transistors being connected in common.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-03-31 | 1978-09-30 | 1979-04-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-03-31 | 1982-09-30 | 1983-04-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-03-31 | 1986-09-30 | 1987-04-01 | $7700.00 | Window Closed / Lapsed |