Method and apparatus for fast evaluation of dynamic CMOS logic circuits

Claim 3

A method as in claim 1 wherein precharging the logic block comprises pulling the clock signal and the delayed clock signal low.

Claim 4

A method as in claim 1 wherein evaluating the logic block comprises pulling the clock signal high.

Claim 5

A method as in claim 1 wherein precharging the logic block comprises pulling an output of the logic block high.

Claim 6

A circuit for precharging and evaluating a logic block of a dynamic logic circuit, the circuit comprising: series connected first and second transistors disposed between a supply voltage and the logic block, the first transistor having a terminal coupled to the supply voltage and a control terminal responsive to a delayed clock signal, and the second transistor having a terminal connected to the logic block and a control terminal responsive to a clock signal; wherein upon a voltage level transition of the clock signal, the delayed clock signal transitions to the same voltage level as the clock signal after a time delay but before a subsequent transition of the clock signal, the logic block being precharged when the clock signal and the delayed clock signal are both at a first voltage level, and evaluated when the clock signal is at a second voltage level.

Claim 7

A circuit for precharging and evaluating a logic block of a dynamic logic circuit, the circuit comprising: series connected first and second transistors disposed between a supply voltage and the logic block, the first transistor having a terminal coupled to the supply voltage and a control terminal responsive to a delayed clock signal, and the second transistor having a terminal connected to the logic block and a control terminal responsive to a clock signal; wherein upon a voltage level transition of the clock signal, the delayed clock signal transitions to the same voltage level as the clock signal after a time delay but before a subsequent transition of the clock signal, the logic block being precharged when the clock signal and the delayed clock signal are both at a first voltage level, and evaluated when the clock signal is at a second voltage level.

Claim 8

A circuit as in claim 5 wherein the first transistor is a PFET device having a source connected to the supply voltage, a gate connected to a delayed clock signal line, and a drain connected to a source of the second transistor.

Claim 9

A circuit as is claim 6 wherein the second transistor is a PFET device having a gate connected to a clock signal line and a drain connected to the logic block.

Claim 10

A circuit as in claim 5 wherein the first and second transistors are stacked.

Claim 11

A circuit as in claim 5 wherein the first transistor is a bipolar device having a collector connected to the supply voltage, a base connected to a delayed clock signal line, and an emitter connected to a collector of the second transistor.

Claim 12

A circuit as in claim 9 wherein the second transistor is a bipolar device having a base connected to a clock signal line and an emitter connected to the logic block.

Claim 13

A domino CMOS logic circuit having a plurality of stages for evaluating logic signals, the domino CMOS logic circuit including at least one stage which has a logic block that includes a plurality of logic devices responsive to at least one input, an output and a precharge circuit for precharging the output, the precharge circuit comprising: a first transistor having a first terminal, a second terminal and a control terminal, the first terminal being coupled to a supply voltage, the control terminal being connected to a delayed clock signal line; a second transistor having a first terminal, a second terminal and a control terminal, the first terminal of the second transistor being coupled to the second terminal of the first transistor, the control terminal of the second transistor being coupled to a clock signal line, and the second terminal of the second transistor being coupled to the output of the logic block; wherein upon a voltage level transition of the clock signal, the delayed clock signal transitions to the same voltage level as the clock signal after a time delay but before a subsequent transition of the clock signal.

Claim 14

A domino CMOS logic circuit having a plurality of stages for evaluating logic signals, the domino CMOS logic circuit including at least one stage which has a logic block that includes a plurality of logic devices responsive to at least one input, an output and a precharge circuit for precharging the output, the precharge circuit comprising: a first transistor having a first terminal, a second terminal and a control terminal, the first terminal being coupled to a supply voltage, the control terminal being connected to a delayed clock signal line; a second transistor having a first terminal, a second terminal and a control terminal, the first terminal of the second transistor being coupled to the second terminal of the first transistor, the control terminal of the second transistor being coupled to a clock signal line, and the second terminal of the second transistor being coupled to the output of the logic block; wherein upon a voltage level transition of the clock signal, the delayed clock signal transitions to the same voltage level as the clock signal after a time delay but before a subsequent transition of the clock signal.

Claim 15

A domino CMOS logic circuit as in claim 11 wherein the first transistor is a field effect device which comprises a source coupled to the supply voltage, a drain, and a gate coupled to the delayed clock signal line.

Claim 16

A domino CMOS logic circuit as in claim 12 wherein the second transistor is a field effect device which comprises a source coupled to the drain of the first transistor, a gate coupled to the clock signal line, and a drain coupled to the outputs of the logic block.

Claim 17

A domino CMOS logic circuit as in claim 11 wherein the first transistor comprises a bipolar device having a collector coupled to the supply voltage, a base coupled to the delayed clock signal line, and an emitter.

Claim 18

A domino CMOS logic circuit as in claim 14 wherein the second transistor comprises a bipolar device having a collector coupled to the emitter of the first transistor, a base coupled to the clock signal line, and a collector coupled to the outputs of the logic block.

Claim 19

A circuit useful in precharging and evaluating a logic block, the circuit comprising: a pair of series connected transistors coupling a supply voltage to a prechargeable output of a logic block, one transistor of the pair having a clock signal coupled to its gate, and the other transistor of the pair having a delayed clock signal coupled to its gate, such that the delayed clock signal transitions to the same voltage level as the clock signal after a time delay but before a subsequent transition of the clock signal; wherein an electrical connection is established between the supply voltage and the prechargeable output when the clock signal and the delayed clock signal are both at a low voltage level, and the electrical connection is broken when the clock signal is at a high voltage level.

Claim 20

A circuit useful in precharging and evaluating a logic block, the circuit comprising: a pair of series connected transistors coupling a supply voltage to a prechargeable output of a logic block, one transistor of the pair having a clock signal coupled to its gate, and the other transistor of the pair having a delayed clock signal coupled to its gate, such that the delayed clock signal transitions to the same voltage level as the clock signal after a time delay but before a subsequent transition of the clock signal; wherein an electrical connection is established between the supply voltage and the prechargeable output when the clock signal and the delayed clock signal are both at a low voltage level, and the electrical connection is broken when the clock signal is at a high voltage level.

Claim 21

A circuit as in claim 16 wherein the output conditionally discharges to ground through a conductive path in the logic block when the clock signal is at a high voltage level, the conductive path being free of any clocked footer devices.