Polyphase logical circuit employing complementary misfet
Abstract
Abstract A COMPLEMENTARY MOS LOGIC CIRCUIT HAS A REDUCED NUMBER OF TRANSISTORS. A P-CHANNEL MOSFET AND AN NCHANNEL MOSFET ARE CONNECTED IN SERIES WITH A LOGICAL BLOCK OF A PREDETERMINED LOGICAL EXPRESSIONS BETWEEN ONE TERMINAL OF A POWER SOURCE AND THE LOGICAL BLOCK AND BETWEEN THE LOGICAL BLOCK AND THE OTHER TERMINAL OF THE POWER SOURCE, RESPECTIVELY. MEANS IS PROVIDED WHICH DRIVES THE P-CHANNEL AND N-CHANNEL MOSFETS BY A FIRST CLOCK PULSE. MEANS IS PROVIDED WHICH ESTABLISHES A CURRENT PATH BETWEEN THE LOGICAL BLOCK AND AN OUTPUT TERMINAL OF THE COMPLEMENTARY MOS LOGICAL CIRCUIT OR BETWEEN THE CONNECTION POINT OF THE LOGICAL BLOCK AND P-CHANNEL MOSFET AND THE OUTPUT TERMINAL AT TIMINGS OF THE FIRST CLOCK PULSE AND A SECOND CLOCK PULSE DIFFERING IN PHASE THEREFROM.
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