Patent US5822776A successfully refreshed from Google Patents.
US5822776A
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Multiplexed random access memory with time division multiplexing through a single read/write port
Assignee: Microsemi Semiconductor ULC
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Filing: 1996-03-11
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Granted: 1998-10-13
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Expires: 2016-03-11
Abstract
Abstract A multiported random access memory (RAM) system comprising a RAM having a data port and an address and control port, plural data buffers each having a bidirectional input port and a bidirectional output port, a data bus connecting the output ports of the data buffers and the data port of the RAM, a multiplexer having plural address and control inputs and an address and control output, the address and control output being connected to the address and control port of the RAM, each of the address and control inputs for receiving address and control data associated with data stored in a specific buffer, a timing apparatus connected to each of the buffers and to a control input of the multiplexer for separately enabling the multiplexer to pass address and control data therethrough to the address and control port of the RAM or to receive data from the data port of the RAM, whereby the bidirectional data input ports of the buffers and each of the corresponding address and control input ports forms a separate time shared port to the RAM.
Inventors
- 👤 Elizias De Korte
- 👤 David Cayer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:26
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G06F13/1673
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
222 words
A multiported random access memory (RAM) system comprising: (a) a RAM having a single read/write data port, and an address and control port, (b) plural data buffers each having a bidirectional input port and a bidirectional output port, (c) a data bus directly connecting the bidirectional output ports of said data buffers to said data port of said RAM, (d) a multiplexer having plural address and control inputs and an address and control output, the address and control output of said multiplexer being directly connected to the address and control port of the RAM, each of the address and control inputs of said multiplexer for receiving address and control data associated with a specific data buffer, (e) a timing means connected to each of the buffers and to a control input of the multiplexer for separately enabling the multiplexer to pass address and control data therethrough to the address and control port of the RAM, at the same time enabling a predetermined buffer to output data via its bidirectional output port that may be stored therein to the data port of the RAM, or to receive data from the data port of the RAM, whereby the bidirectional data input ports of the buffers and each of the corresponding address and control input ports forms a separate time shared port to the RAM.
Claim 2
Dependent Claim
222 words
A multiported random access memory (RAM) system comprising: (a) a RAM having a single read/write data port, and an address and control port, (b) plural data buffers each having a bidirectional input port and a bidirectional output port, (c) a data bus directly connecting the bidirectional output ports of said data buffers to said data port of said RAM, (d) a multiplexer having plural address and control inputs and an address and control output, the address and control output of said multiplexer being directly connected to the address and control port of the RAM, each of the address and control inputs of said multiplexer for receiving address and control data associated with a specific data buffer, (e) a timing means connected to each of the buffers and to a control input of the multiplexer for separately enabling the multiplexer to pass address and control data therethrough to the address and control port of the RAM, at the same time enabling a predetermined buffer to output data via its bidirectional output port that may be stored therein to the data port of the RAM, or to receive data from the data port of the RAM, whereby the bidirectional data input ports of the buffers and each of the corresponding address and control input ports forms a separate time shared port to the RAM.
Claim 3
Dependent Claim
71 words
A RAM system as defined in claim 1 wherein the output signal of the timing circuit is a binary signal comprising a cycling count whereby the multiplexer is controlled thereby in sequence to pass address and control data from each of its inputs in sequence to its address and control output, and wherein each of the buffers is controlled in sequence to output or receive data via its bidirectional output port.
Claim 4
Dependent Claim
65 words
A RAM system as defined in claim 2 wherein a cycle time of said count defines a frame having an interval which is equal to the number of buffers multiplied by a time slot, each time slot being a time period which is at least as long as a longest cycle time of either the data, or the address and control port of the RAM.
Claim 5
Dependent Claim
168 words
A multiplexed random access memory (RAM) system comprising: (a) a RAM having a single read/write data port and an address and control port, (b) plural buffers, each comprising a bidirectional data input port and a bidirectional data output port, an address and control input port and an address and control output port, (c) means for latching address and control signals received via the address and control input ports of the buffer, (d) the bidirectional data output ports of the buffers being connected to the address and control port of the RAM, (e) a timing means connected to each of the buffers for generating a cyclic count signal and thereby enabling each buffer in sequence to release latched addresses and control signals and data stored therein to the address and control input and to the data port respectively of the RAM, whereby the bidirectional data input ports of the buffers and each of the corresponding address and control input ports form a separate time shared port to the RAM.
Claim 6
Dependent Claim
168 words
A multiplexed random access memory (RAM) system comprising: (a) a RAM having a single read/write data port and an address and control port, (b) plural buffers, each comprising a bidirectional data input port and a bidirectional data output port, an address and control input port and an address and control output port, (c) means for latching address and control signals received via the address and control input ports of the buffer, (d) the bidirectional data output ports of the buffers being connected to the address and control port of the RAM, (e) a timing means connected to each of the buffers for generating a cyclic count signal and thereby enabling each buffer in sequence to release latched addresses and control signals and data stored therein to the address and control input and to the data port respectively of the RAM, whereby the bidirectional data input ports of the buffers and each of the corresponding address and control input ports form a separate time shared port to the RAM.
Claim 7
Dependent Claim
66 words
A RAM system as defined in claim 4 wherein a cycle time of said cyclic count signal defines a frame having an interval which is equal to the number of buffers multiplied by a time slot, each time slot being a time period which is at least as long as a longest cycle time of either the data, or address and control port of the RAM.
Claim 8
Dependent Claim
130 words
A multiplexed random access memory (RAM) comprising: (a) a RAM having a single read/write data port and an address and control port, (b) plural data storing means connected to the data port, and (c) means for addressing the RAM and for controlling the inputting or outputting of data to or from each of said plural data storing means in a sequential manner to or from separately addressed RAM memory locations, said addressing means being comprised of a multiplexer for receiving address and control signals each relating to data stored in a respective one of the data storing means and for applying one of the address and control signals to the RAM while enabling one of the plural data storing means to apply or receive data to or from the RAM.
Claim 9
Dependent Claim
130 words
A multiplexed random access memory (RAM) comprising: (a) a RAM having a single read/write data port and an address and control port, (b) plural data storing means connected to the data port, and (c) means for addressing the RAM and for controlling the inputting or outputting of data to or from each of said plural data storing means in a sequential manner to or from separately addressed RAM memory locations, said addressing means being comprised of a multiplexer for receiving address and control signals each relating to data stored in a respective one of the data storing means and for applying one of the address and control signals to the RAM while enabling one of the plural data storing means to apply or receive data to or from the RAM.
Claim 10
Dependent Claim
80 words
A RAM as defined in claim 6 in which the addressing means is comprised of a plurality of latch means each associated with a data storing means for storing address and control signals relating to data stored in an associated data storing means, and means for enabling the data storing means and an associated latch means for applying one of the address and control signals and associated data stored in the data storing means to corresponding ports of the RAM.
Claim 11
Independent Claim
89 words
A method of operating a random access memory (RAM) having a single read/write data port and an address and control port comprising the steps of providing a sequence of different address and control signals to the address and control port of the RAM for sequentially addressing different storage locations of the RAM, and inputting or receiving data relating to plural data ports, to or from the data port of the RAM, whereby storage or retrieval of data to or from the data port of the RAM is time shared.
Claim 12
Independent Claim
89 words
A method of operating a random access memory (RAM) having a single read/write data port and an address and control port comprising the steps of providing a sequence of different address and control signals to the address and control port of the RAM for sequentially addressing different storage locations of the RAM, and inputting or receiving data relating to plural data ports, to or from the data port of the RAM, whereby storage or retrieval of data to or from the data port of the RAM is time shared.
Claim 13
Dependent Claim
40 words
A method as defined in claim 8 including providing said sequence of different address and control signals through a multiplexer and controlling the multiplexer in time with said inputting to, or receiving data from the data port of the RAM.
Claim 14
Dependent Claim
42 words
A method as defined in claim 8 including storing each address and associated control signals in a latch means, and enabling each latch means in sequence and in time with said inputting or receiving data from the data port of the RAM.
Claim 15
Dependent Claim
46 words
A method as defined in claim 9 including storing data relating to said plural data ports in separate buffers, bidirectional data input ports of said buffers each forming a data port with access to the RAM data port time shared with other bidirectional data input ports.
Claim 16
Dependent Claim
56 words
A method as defined in claim 10 including storing data relating to said plural data ports in separate buffers, each buffer being associated with a corresponding said latch means, bidirectional data input ports of said buffers each forming a data port with access to the RAM data port time shared with other bidirectional data input ports.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-12 | 2002-04-13 | 2002-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-12 | 2006-04-13 | 2006-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-12 | 2010-04-13 | 2010-10-13 | $7700.00 | Window Closed / Lapsed |