US5822387A
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US
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Apparatus for fast phase-locked loop (PLL) frequency slewing during power on
Assignee: Callahan Cellular LLC
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Filing: 1996-03-25
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Granted: 1998-10-13
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Expires: 2016-03-25
Abstract
Abstract A clock synthesizer is disclosed that includes a phase-locked loop circuit having two modes of operation: a non-slewing mode of operation, and a frequency-slewing mode of operation. During the power-up of the system, the PLL is controlled to operate in the non-slewing mode of operation to effect rapid variations in the output frequency. A power-on reset circuit is disclosed which determines when the system is in the power-up interval, and generates a power-on-reset signal to so indicate. The PLL operates in a frequency-slewing mode after power-up to provide controlled transitions in the frequency of the output reference signal of the PLL. A phase-locked loop circuit having structure to implement both modes is provided, as well as an adjustable lock detector circuit. The output of the lock detector, a logical lock signal, is used to enable the frequency-slewing mode of the PLL circuit. During power-up, the power-on-reset signal is deasserted, and disables the lock detector from generating the frequency-slewing mode enable signal. The PLL thus operates in a non-slewing mode during power-up. After the power-on-reset signal has been asserted, the lock detector is permitted to generate the frequency-mode enable signal as soon as the PLL achieves phase lock. Once phase lock has been achieved, the enable signal from the lock detector places the PLL in a frequency-slewing mode. The phase-locked loop circuit includes structure that limits the rate of variation in the frequency of the output reference signal, as well as limits the UP, and DOWN signals, by way of a reference window signal mechanism, to ensure that the lock detector, after power-up, always detects lock to thereby generate the frequency-slewing mode enable signal.
Inventors
- 👤 Monte F. Mar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:21
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/095; H03L3/00; H03L7/07; H03L7/089; H03L7/0891
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
201 words
An apparatus for generating an output reference signal using an input reference signal, comprising: a primary phase-locked loop (PLL) circuit responsive to the input reference signal for generating the output reference signal, said primary PLL circuit including means for generating a first actual out-of-lock indicative signal indicative of the extent to which said primary PLL is out-of-lock; means responsive to said first actual out-of-lock indicative signal for generating a first gated out-of-lock indicative signal which, when in a non-slewing mode of operation, corresponds to said first actual out-of-lock indicative signal, and, when in a frequency-slewing mode of operation, corresponds to said first actual out-of-lock indicative signal modified according to a predetermined strategy so as to limit a rate at which the output reference signal varies, said first gated out-of-lock indicative signal generating means being selectable for operation in one of said non-slewing and frequency-slewing modes according to an enable signal; and, a primary lock detector circuit for generating said enable signal when said gated out-of-lock indicative signal indicates that said output reference signal is locked to the input reference signal within a first predetermined error margin, said primary lock detector being responsive to a disable signal for disabling said enable signal.
Claim 2
Independent Claim
201 words
An apparatus for generating an output reference signal using an input reference signal, comprising: a primary phase-locked loop (PLL) circuit responsive to the input reference signal for generating the output reference signal, said primary PLL circuit including means for generating a first actual out-of-lock indicative signal indicative of the extent to which said primary PLL is out-of-lock; means responsive to said first actual out-of-lock indicative signal for generating a first gated out-of-lock indicative signal which, when in a non-slewing mode of operation, corresponds to said first actual out-of-lock indicative signal, and, when in a frequency-slewing mode of operation, corresponds to said first actual out-of-lock indicative signal modified according to a predetermined strategy so as to limit a rate at which the output reference signal varies, said first gated out-of-lock indicative signal generating means being selectable for operation in one of said non-slewing and frequency-slewing modes according to an enable signal; and, a primary lock detector circuit for generating said enable signal when said gated out-of-lock indicative signal indicates that said output reference signal is locked to the input reference signal within a first predetermined error margin, said primary lock detector being responsive to a disable signal for disabling said enable signal.
Claim 3
Dependent Claim
35 words
The apparatus of claim 1 further comprising a power-on-reset circuit for generating said disable signal during a power-up phase of a power supply until an output of said power supply has reached a preselected level.
Claim 4
Dependent Claim
77 words
The apparatus of claim 2 wherein said power-on-reset circuit includes: a secondary phase-locked loop (PLL) circuit including means for generating a second actual out-of-lock indicative signal indicative of the extent to which said secondary PLL circuit is out-of-lock; a secondary lock detector circuit responsive to said second actual out-of-lock indicative signal for generating said disable signal when said second actual out-of-lock indicative signal indicates that said secondary PLL is locked to within a second predetermined error margin.
Claim 5
Dependent Claim
75 words
The apparatus of claim 3 wherein said secondary PLL further includes: means responsive to said second actual out-of-lock indicative signal for generating a second gated out-of-lock indicative signal which, when in a non-slewing mode of operation of said secondary PLL, corresponds to said second actual out-of-lock indicative signal, and, when in a frequency-slewing mode of operation of said secondary PLL, corresponds to said second actual out-of-lock indicative signal modified according to a second predetermined strategy.
Claim 6
Dependent Claim
19 words
The apparatus of claim 3 wherein said second predetermined error margin is larger than said first predetermined error margin.
Claim 7
Dependent Claim
18 words
The apparatus of claim 1 wherein said first actual out-of-lock indicative signal generating means includes a phase/frequency detector.
Claim 8
Dependent Claim
42 words
The apparatus of claim 1 wherein said first actual out-of-lock indicative signal comprises an UP signal indicating that the output reference signal lags the input reference signal, and a DOWN signal indicating that the output reference signal leads the input reference signal.
Claim 9
Dependent Claim
62 words
The apparatus of claim 1 wherein said first gated out-of-lock indicative signal generating means includes means for generating a reference window signal about the input reference signal, and, an AND gate responsive to said first actual out-of-lock indicative signal and said window signal for restricting said first actual out-of-lock indicative signal to be active within an active portion of said window signal.
Claim 10
Dependent Claim
45 words
The apparatus of claim 1 wherein said predetermined strategy includes ensuring that said first gated out-of-lock indicative signal, when in said frequency slewing mode, is generated to indicate lock within said first predetermined error margin to thereby maintain said enable signal in an active state.
Claim 11
Independent Claim
326 words
An apparatus for generating an output reference signal using an input reference signal, comprising: a phase/frequency detector responsive to the output and input reference signals for generating an actual out-of-lock indicative signal indicating the extent to which the output reference signal is out-of-lock relative to the input reference signal; means responsive to said actual out-of-lock indicative signal for generating a gated out-of-lock indicative signal; means for generating the output reference signal according to said gated out-of-lock indicative signal; a lock detector for generating a frequency-slewing enable signal when said gated out-of-lock indicative signal indicates that the output reference signal is locked to the input reference signal within a predetermined error margin, said enable signal generating means disabling said enable signal according to a disable signal provided thereto; said gated out-of-lock generating means being operative for passing said actual out-of-lock indicative signal to said output reference signal generating means in a non-slewing mode of operation, and for limiting said actual out-of-lock indicative signal in a frequency-slewing mode of operation according to a predetermined strategy such that said gated out-of-lock indicative signal indicates lock within said predetermined error margin to thereby maintain generation of said enable signal by said lock detector, said gated out-of-lock indicative signal generator means being operable in a selected one of said non-slewing and frequency-slewing modes of operation according to said enable signal; said means for generating said gated out-of-lock indicative signal being in said non-slewing mode of operation when said disable signal is present wherein said output reference signal is generated using said actual out-of-lock indicative signal to thereby effect fast output reference signal variations; said means for generating said gated out-of-lock indicative signal being in said frequency-slewing mode of operation when said enable signal is generated wherein said output reference signal is generated using said gated out-of-lock indicative signal as limited by said predetermined strategy to thereby effect controlled variations of said output reference signal whereby two modes of operation are provided.
Claim 12
Independent Claim
326 words
An apparatus for generating an output reference signal using an input reference signal, comprising: a phase/frequency detector responsive to the output and input reference signals for generating an actual out-of-lock indicative signal indicating the extent to which the output reference signal is out-of-lock relative to the input reference signal; means responsive to said actual out-of-lock indicative signal for generating a gated out-of-lock indicative signal; means for generating the output reference signal according to said gated out-of-lock indicative signal; a lock detector for generating a frequency-slewing enable signal when said gated out-of-lock indicative signal indicates that the output reference signal is locked to the input reference signal within a predetermined error margin, said enable signal generating means disabling said enable signal according to a disable signal provided thereto; said gated out-of-lock generating means being operative for passing said actual out-of-lock indicative signal to said output reference signal generating means in a non-slewing mode of operation, and for limiting said actual out-of-lock indicative signal in a frequency-slewing mode of operation according to a predetermined strategy such that said gated out-of-lock indicative signal indicates lock within said predetermined error margin to thereby maintain generation of said enable signal by said lock detector, said gated out-of-lock indicative signal generator means being operable in a selected one of said non-slewing and frequency-slewing modes of operation according to said enable signal; said means for generating said gated out-of-lock indicative signal being in said non-slewing mode of operation when said disable signal is present wherein said output reference signal is generated using said actual out-of-lock indicative signal to thereby effect fast output reference signal variations; said means for generating said gated out-of-lock indicative signal being in said frequency-slewing mode of operation when said enable signal is generated wherein said output reference signal is generated using said gated out-of-lock indicative signal as limited by said predetermined strategy to thereby effect controlled variations of said output reference signal whereby two modes of operation are provided.
Claim 13
Dependent Claim
35 words
The apparatus of claim 10 further including a power-on-reset circuit for generating said disable signal during a power-up phase of a power supply until an output of said power supply has reached a preselected level.
Claim 14
Dependent Claim
41 words
The apparatus of claim 10 wherein said actual out-of-lock indicative signal comprises an UP signal indicating that the output reference signal lags the input reference signal, and a DOWN signal indicating that the output reference signal leads the input reference signal.
Claim 15
Dependent Claim
17 words
The apparatus of claim 10 wherein said gated out-of-lock indicative signal generating means includes an AND gate.
Claim 16
Dependent Claim
44 words
The apparatus of claim 10 wherein said output reference signal generating means includes a charge pump for generating a control signal corresponding to a desired output reference signal, and a voltage-controlled oscillator (VCO) responsive to said control signal for generating the output reference signal.
Claim 17
Dependent Claim
29 words
The apparatus of claim 14 wherein said output reference signal generating means further includes a loop filter for filtering said control signal in accordance with a predetermined transfer function.
Claim 18
Dependent Claim
298 words
A clock synthesizer device having fast frequency slewing during power-on, comprising: a primary phase-locked loop (PLL) circuit responsive to an input reference signal for generating an output reference signal, said primary PLL circuit including means for generating a first actual out-of-lock indicative signal indicative of the extent to which said primary PLL is out-of-lock; means responsive to said first actual out-of-lock indicative signal for generating a first gated out-of-lock indicative signal which, when in a non-slewing mode of operation, corresponds to said first actual out-of-lock indicative signal, and, when in a frequency-slewing mode of operation, corresponds to said first actual out-of-lock indicative signal modified according to a predetermined strategy so as to limit a rate at which the output reference signal varies, said first gated out-of-lock indicative signal generating means being selectable for operation in one of said non-slewing and frequency-slewing modes according to an enable signal; a primary lock detector circuit for generating said enable signal when said gated out-of-lock indicative signal indicates that said output reference signal is locked to the input reference signal within a first predetermined error margin, said primary lock detector being responsive to a power-on-reset signal for disabling generation of said enable signal; a power-on-reset circuit for generating said power-on-reset signal during a power-up phase of a power supply until an output of said power supply has reached a preselected level, said power-on-reset circuit including a secondary phase-locked loop (PLL) circuit including means for generating a second actual out-of-lock indicative signal indicative of the extent to which said secondary PLL circuit is out-of-lock; a secondary lock detector circuit responsive to said second actual out-of-lock indicative signal for generating said power-on-reset signal when said second actual out-of-lock indicative signal indicates that said secondary PLL is locked to within a second predetermined error margin.
Claim 19
Dependent Claim
298 words
A clock synthesizer device having fast frequency slewing during power-on, comprising: a primary phase-locked loop (PLL) circuit responsive to an input reference signal for generating an output reference signal, said primary PLL circuit including means for generating a first actual out-of-lock indicative signal indicative of the extent to which said primary PLL is out-of-lock; means responsive to said first actual out-of-lock indicative signal for generating a first gated out-of-lock indicative signal which, when in a non-slewing mode of operation, corresponds to said first actual out-of-lock indicative signal, and, when in a frequency-slewing mode of operation, corresponds to said first actual out-of-lock indicative signal modified according to a predetermined strategy so as to limit a rate at which the output reference signal varies, said first gated out-of-lock indicative signal generating means being selectable for operation in one of said non-slewing and frequency-slewing modes according to an enable signal; a primary lock detector circuit for generating said enable signal when said gated out-of-lock indicative signal indicates that said output reference signal is locked to the input reference signal within a first predetermined error margin, said primary lock detector being responsive to a power-on-reset signal for disabling generation of said enable signal; a power-on-reset circuit for generating said power-on-reset signal during a power-up phase of a power supply until an output of said power supply has reached a preselected level, said power-on-reset circuit including a secondary phase-locked loop (PLL) circuit including means for generating a second actual out-of-lock indicative signal indicative of the extent to which said secondary PLL circuit is out-of-lock; a secondary lock detector circuit responsive to said second actual out-of-lock indicative signal for generating said power-on-reset signal when said second actual out-of-lock indicative signal indicates that said secondary PLL is locked to within a second predetermined error margin.
Claim 20
Dependent Claim
19 words
The apparatus of claim 16 wherein said second predetermined error margin is larger than said first predetermined error margin.
Claim 21
Dependent Claim
13 words
The apparatus of claim 16 wherein said first predetermined error margin is adjustable.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-12 | 2002-04-13 | 2002-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-12 | 2006-04-13 | 2006-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-12 | 2010-04-13 | 2010-10-13 | $7700.00 | Window Closed / Lapsed |