US3795870A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Adaptive bandwidth phase lock loop employing high speed loop lock and fast phase transient reduction
Assignee: HP Inc
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Filing: 1972-10-30
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Granted: 1974-03-05
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Expires: 1992-10-30
Abstract
Abstract A phase lock loop system employing a frequency-phase detector circuit operating in the frequency detector mode to produce a high level dc control signal to the VCO of the loop to slew the VCO rapidly to lock the loop, the bandwidth of the loop being relatively wide before the loop reaches steady-state lock thereby to reduce the phase transient to the steady-state lock at a rapid rate, the loop bandwidth at steady-state being lower in value and at an optimum value for good noise characteristics. At loop lock, the frequency/phase detector circuit switches to its phase detector mode of operation for normal phase lock loop operation. Speed up of loop lock is accomplished by the enabling of a variable high gain amplifier during off lock to substantially increase the output level of the phase detector to the VCO tuning circuitry.
Inventors
- 👤 S Sanders
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:12
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/10; H03L7/107; H03L7/1075
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
222 words
A phase lock loop for locking to a reference frequency derived from a reference signal, the phase lock loop comprising: a variable frequency signal source having a tuning input and a signal output, the frequency of the output signal being controlled by a signal on the tuning input; a frequency/phase detector having a first input connected to receive the signal source output signal and a second input connected to receive the reference signal, having a signal output for giving a signal indicative of the phase between the reference frequency and the signal source output frequency when those two frequencies are equal and for giving a signal indicative of the algebraic sign of the difference between the reference frequency and the signal source output frequency when these two frequencies are not equal, and having an enable output for giving a signal that indicates when the reference frequency and the signal source output frequency are not equal; and control means connected to the signal source tuning input, the frequency/phase detector signal output and the enable output for providing a signal path between the frequency/phase detector signal output and the signal source tuning input having a first gain and bandwidth when the reference frequency and the signal source output frequency are equal and a second gain and bandwidth when those two frequencies are not equal.
Claim 2
Dependent Claim
222 words
A phase lock loop for locking to a reference frequency derived from a reference signal, the phase lock loop comprising: a variable frequency signal source having a tuning input and a signal output, the frequency of the output signal being controlled by a signal on the tuning input; a frequency/phase detector having a first input connected to receive the signal source output signal and a second input connected to receive the reference signal, having a signal output for giving a signal indicative of the phase between the reference frequency and the signal source output frequency when those two frequencies are equal and for giving a signal indicative of the algebraic sign of the difference between the reference frequency and the signal source output frequency when these two frequencies are not equal, and having an enable output for giving a signal that indicates when the reference frequency and the signal source output frequency are not equal; and control means connected to the signal source tuning input, the frequency/phase detector signal output and the enable output for providing a signal path between the frequency/phase detector signal output and the signal source tuning input having a first gain and bandwidth when the reference frequency and the signal source output frequency are equal and a second gain and bandwidth when those two frequencies are not equal.
Claim 3
Dependent Claim
22 words
A phase lock loop as in claim 1 wherein the second gain and bandwidth are greater than the first gain and bandwidth.
Claim 4
Dependent Claim
45 words
A phase lock loop as in claim 2 wherein the gain and bandwidth of the signal path decrease gradually from the second to the first values after the signal source output frequency becomes equal to the reference frequency as the phase lock loop becomes locked.
Claim 5
Dependent Claim
74 words
A phase lock loop as in claim 3 wherein the control means comprises: a first and a second filter network cOnnected in series between the frequency/phase detector signal output and the signal source tuning input; and a variable gain amplifier connected in parallel with the first filter network and having an enable input connected to the frequency/phase detector enable output, the gain of the amplifier being responsive to the signal at the enable output.
Claim 6
Dependent Claim
125 words
A phase lock loop as in claim 4 wherein the reference frequency is a rational fraction of the frequency of the reference signal and the frequency/phase detector includes: a divide by N counter connected to receive the reference signal for dividing the frequency of the reference signal by an integer N; a divide by M counter connected to receive the signal source output for driving the frequency of the signal source output by an integer M; and circuit means connected to the divide by N and divide by M counters and to the frequency/phase detector signal and enable outputs for comparing and giving output signals indicative of the frequency and phase of the output signals from the divide by N and divide by M counters.
Claim 7
Dependent Claim
54 words
A phase lock loop as in claim 5 wherein the signal source includes: a signal controlled oscillator having a tuning input and a signal output; and a frequency converter having inputs connected to receive the oscillator output signal and an intermediate frequency signal and having an output connected to the signal source signal output.
Claim 8
Dependent Claim
64 words
A phase lock loop as in claim 6 wherein the control means includes an energy storage device connected to the signal source tuning input for providing a voltage tuning signal for the signal tuned oscillator; and the circuit means provides a constant current to the energy storage device via the variable gain amplifier when the signal source output frequency differs from the reference frequency.
References Cited (Backward Citations)
US3441871A
Cited
US3611175A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-03-04 | 1977-09-03 | 1978-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-03-04 | 1981-09-03 | 1982-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-03-04 | 1985-09-03 | 1986-03-05 | $7700.00 | Window Closed / Lapsed |