Patent US5821818A successfully refreshed from Google Patents.
US5821818A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase locked loop ciruit for a liquid crystal display
Assignee: International Business Machines Corp
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Filing: 1996-11-26
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Granted: 1998-10-13
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Expires: 2016-11-26
Abstract
Abstract This single voltage controlled oscillator for a PLL circuit has two control loops: a low noise ration is maintained by a main loop; while a wide frequency capture range is ensured by a sub-loop controlled by a one-chip microcomputer. The main control loop is a low gain loop with a narrow capture range that compares the phase of the output of the PLL circuit with the phase of a horizontal synchronous video signal supplied to a LCD display. The sub-loop is a high gain loop with a broad frequency range that includes a processor that monitors the lock on the main loop. When the lock is broken, the processor increments or decrements the voltage supplied to this sub-loop in one or more steps until the lock is reestablished, and the PLL circuit is again operating within the narrow capture range of the low gain loop.
Inventors
- 👤 Seiichi Idei
- 👤 Takuya Ishikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:36
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/08; H03L7/099; H03L7/10; G; G09; G09G; G09G3/00; G09G3/20; G09G3/34; G09G3/36; G09G3/3611; G09G5/00; G09G5/18; H03L2207/00; H03L2207/06; Y; Y10; Y10S; Y10S331/00; Y10S331/02
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
241 words
A circuit for generating a dot-clock signal synchronized with a horizontal video synchronization signal for multiple display modes comprising: voltage controlled oscillator that provides an output signal that varies in frequency with the magnitude of control voltages provided to inputs of the voltage controlled oscillator; a variable frequency divider for dividing the output signal of said voltage controlled oscillator at a predetermined but changeable frequency division ratio which depends on the display mode; a phase comparator comparing the phase of the output of said variable frequency divider with the phase of the horizontal video synchronization signal and providing an output indicative of the phase difference; a fine control loop coupling the inputs of the voltage controlled oscillator to the output of the comparator to provide a first input control voltage to the voltage controlled oscillator, said fine control loop being a phase locked loop circuit with a low conversion gain to maintain a low noise ratio when a lock for the phase locked loop circuit is locked; detection means for determining whether the lock on the phase locked loop circuit is released; and a coarse control loop including the detection means coupling the inputs of the oscillator to the output of the phase comparator for providing, only when the detection means indicates the lock is released, a change in a second input control voltage to the voltage controlled oscillator through a high conversion gain path with a wide variable frequency range.
Claim 2
Dependent Claim
241 words
A circuit for generating a dot-clock signal synchronized with a horizontal video synchronization signal for multiple display modes comprising: voltage controlled oscillator that provides an output signal that varies in frequency with the magnitude of control voltages provided to inputs of the voltage controlled oscillator; a variable frequency divider for dividing the output signal of said voltage controlled oscillator at a predetermined but changeable frequency division ratio which depends on the display mode; a phase comparator comparing the phase of the output of said variable frequency divider with the phase of the horizontal video synchronization signal and providing an output indicative of the phase difference; a fine control loop coupling the inputs of the voltage controlled oscillator to the output of the comparator to provide a first input control voltage to the voltage controlled oscillator, said fine control loop being a phase locked loop circuit with a low conversion gain to maintain a low noise ratio when a lock for the phase locked loop circuit is locked; detection means for determining whether the lock on the phase locked loop circuit is released; and a coarse control loop including the detection means coupling the inputs of the oscillator to the output of the phase comparator for providing, only when the detection means indicates the lock is released, a change in a second input control voltage to the voltage controlled oscillator through a high conversion gain path with a wide variable frequency range.
Claim 3
Dependent Claim
32 words
The circuit according to claim 1, wherein said detection means periodically monitors the output level of the comparator for detecting whether said lock of the phase locked loop circuit has been released.
Claim 4
Dependent Claim
15 words
The circuit according to claim 2, wherein said voltage controlled oscillator is an LC oscillator.
Claim 5
Dependent Claim
33 words
The circuit according to claim 3 including a first voltage controlled capacitor in the fine control loop, said first voltage controlled capacitor having a narrow dynamic range that when exceeded releases the lock.
Claim 6
Dependent Claim
26 words
The circuit according to claim 4 including a second voltage controlled capacitor in the coarse control loop, said second controlled capacitor having a broad dynamic range.
Claim 7
Dependent Claim
75 words
The circuit according to claim 5 wherein said detection means includes a microprocessor which periodically checks for release of the lock providing a pulse output each time release of the lock is detected and means responsive to the pulse output providing a signal thru a low pass filter to the second voltage controlled capacitor to periodically change the frequency of the output signal provided by the oscillator unless the phase lock loop circuit is locked.
Claim 8
Dependent Claim
209 words
A circuit or generating a dot-clock signal synchronized with a horizontal synchronization signal of a video display comprising: a voltage controlled oscillator that provides an output signal that varies in frequency with control voltages applied thereto, said voltage controlled oscillator having a first voltage controlled capacitor with a narrow dynamic range and a second voltage controlled capacitor with a broad dynamic range; a variable frequency divider that divides the output signal of the voltage controlled oscillator at a changeable division ratio; a phase comparator that compares the phase of the output of the variable frequency divider with the phase of the horizontal video signal providing an output indicative of the phase difference; a phase locked loop circuit with a low conversion gain coupling the output of the phase comparator to the first voltage controlled capacitor to maintain a low noise ration when a lock for the phase locked loop circuit is locked; a coarse control loop with a high conversion gain including a processor means that periodically checks for release of the lock for providing incremental changes in a voltage applied to the second voltage controlled capacitor to change the frequency of the oscillator output unless a check for the release of the lock indicates the lock is locked.
Claim 9
Dependent Claim
209 words
A circuit or generating a dot-clock signal synchronized with a horizontal synchronization signal of a video display comprising: a voltage controlled oscillator that provides an output signal that varies in frequency with control voltages applied thereto, said voltage controlled oscillator having a first voltage controlled capacitor with a narrow dynamic range and a second voltage controlled capacitor with a broad dynamic range; a variable frequency divider that divides the output signal of the voltage controlled oscillator at a changeable division ratio; a phase comparator that compares the phase of the output of the variable frequency divider with the phase of the horizontal video signal providing an output indicative of the phase difference; a phase locked loop circuit with a low conversion gain coupling the output of the phase comparator to the first voltage controlled capacitor to maintain a low noise ration when a lock for the phase locked loop circuit is locked; a coarse control loop with a high conversion gain including a processor means that periodically checks for release of the lock for providing incremental changes in a voltage applied to the second voltage controlled capacitor to change the frequency of the oscillator output unless a check for the release of the lock indicates the lock is locked.
Claim 10
Dependent Claim
26 words
The circuit of claim 7 including a processor means that sets the division ratio of the variable frequency divider as a function of the display mode.
Claim 11
Dependent Claim
32 words
The circuit of claim 8 including an EEPROM storing predetermined frequency ratios to provide to the processor to establish the division ratio of the variable frequency divider suitable for the display resolution.
Claim 12
Dependent Claim
25 words
The circuit of claim 9 including a digital to analog converter for generating the incremental changes in voltage from digital signals provided by the processor.
Claim 13
Dependent Claim
37 words
The circuit of claim 10 wherein the EEPROM includes stored values used to advance the output of the digital to analog converter to a default value when there is a change in the display mode of operation.
Claim 14
Dependent Claim
34 words
The circuit of claim 11 including a low pass filter in the coarse control loop to filter the output of the digital to analog converter to minimize the effect of noise on the oscillator.
References Cited (Backward Citations)
US4131862A
Cited
US4213096A
Cited
US4513448A
Cited
US5036295A
Cited
US5254958A
Cited
US5124671A
Cited
US5408196A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-12 | 2002-04-13 | 2002-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-12 | 2006-04-13 | 2006-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-12 | 2010-04-13 | 2010-10-13 | $7700.00 | Window Closed / Lapsed |