Patent US5821788A successfully refreshed from Google Patents.
US5821788A
Expired / Lapsed
US
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Zero consumption power-on-reset
Assignee: STMicroelectronics SRL
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Filing: 1997-01-30
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Granted: 1998-10-13
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Expires: 2017-01-30
Abstract
Abstract A power-on-reset (P.O.R.) circuit produces a power-on-reset (P.O.R.) signal whose an amplitude tracks the voltage on a supply node until it exceeds a certain threshold. The circuit has a first monitoring and comparing circuit portion including at least a nonvolatile memory element having a control gate coupled to the supply node, a first current terminal coupled to a ground node, and a second current terminal coupled to a first node which is capacitively coupled to the supply node. The circuit further includes a second circuit portion that includes an intrinsically unbalanced bistable circuit, having a node that intrinsically is in a high state at power-on coupled to the first node that is intrinsically in a low state at power-on coupled to the input of an output buffer.
Inventors
- 👤 Luigi Pascucci
- 👤 Paolo Rolandi
- 👤 Marco Fontana
- 👤 Antonio Barcella
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 04:41
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/143
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
145 words
A power-on-reset (P.O.R.) circuit comprising: first monitoring and comparing means for a voltage on a supply node; second means producing a power-on-reset (P.O.R.) signal with an amplitude that tracks the voltage on the supply node until it exceeds a certain threshold; and an output buffer having an input; said first monitoring and comparing means comprising at least one nonvolatile memory element having a control gate coupled to the supply node, and a first current terminal coupled to a ground node and a second current terminal coupled to a first node which is capacitively coupled to the supply node; said second means comprising an intrinsically unbalanced bistable circuit having a node that intrinsically is in a high state at power-on coupled to said first node, and having a node that intrinsically is in a low state at power-on coupled to the input of said output buffer.
Claim 2
Dependent Claim
145 words
A power-on-reset (P.O.R.) circuit comprising: first monitoring and comparing means for a voltage on a supply node; second means producing a power-on-reset (P.O.R.) signal with an amplitude that tracks the voltage on the supply node until it exceeds a certain threshold; and an output buffer having an input; said first monitoring and comparing means comprising at least one nonvolatile memory element having a control gate coupled to the supply node, and a first current terminal coupled to a ground node and a second current terminal coupled to a first node which is capacitively coupled to the supply node; said second means comprising an intrinsically unbalanced bistable circuit having a node that intrinsically is in a high state at power-on coupled to said first node, and having a node that intrinsically is in a low state at power-on coupled to the input of said output buffer.
Claim 3
Dependent Claim
66 words
A P.O.R. circuit according to claim 1, wherein said intrinsically unbalanced bistable circuit comprises two cross-coupled inverting stages, a first stage comprising a pair of complementary, enhancement type transistors and having an output node coupled to said first node, a second stage comprising a pair of complementary transistors having a substantially unmodified threshold and having an output node coupled to the input of said output buffer.
Claim 4
Dependent Claim
44 words
A P.O.R. circuit according to claim 1, further comprising a pass transistor having a gate coupled to the supply node; and wherein the second current terminal of said at least one nonvolatile memory element is coupled to said first node through said pass transistor.
Claim 5
Dependent Claim
53 words
A P.O.R. circuit according to claim 2, wherein said nonvolatile memory element comprises a diffusion coinciding with the second current terminal thereof; wherein the two inverting stages comprise respective diffusions coinciding with the output nodes thereof; and wherein each of said diffusions have an incremented area to increase a relative junction capacitance thereof.
Claim 6
Dependent Claim
176 words
A nonvolatile memory device comprising: an array of nonvolatile memory cells; a redundancy circuit including rows of registers for redundancy addresses; a plurality of power-on-reset circuits to initialize said rows of registers, each power-on-reset circuit comprising first monitoring and comparing means for a voltage on a supply node; second means producing a power-on-reset (P.O.R.) signal with an amplitude that tracks the voltage on the supply node until it exceeds a certain threshold; and an output buffer having an input; said first monitoring and comparing means comprising at least one nonvolatile memory element having a control gate coupled to the supply node, and a first current terminal coupled to a ground node and a second current terminal coupled to a first node which is capacitively coupled to the supply node; said second means comprising an intrinsically unbalanced bistable circuit having a node that intrinsically is in a high state at power-on coupled to said first node, and having a node that intrinsically is in a low state at power-on coupled to the input of said output buffer.
Claim 7
Dependent Claim
176 words
A nonvolatile memory device comprising: an array of nonvolatile memory cells; a redundancy circuit including rows of registers for redundancy addresses; a plurality of power-on-reset circuits to initialize said rows of registers, each power-on-reset circuit comprising first monitoring and comparing means for a voltage on a supply node; second means producing a power-on-reset (P.O.R.) signal with an amplitude that tracks the voltage on the supply node until it exceeds a certain threshold; and an output buffer having an input; said first monitoring and comparing means comprising at least one nonvolatile memory element having a control gate coupled to the supply node, and a first current terminal coupled to a ground node and a second current terminal coupled to a first node which is capacitively coupled to the supply node; said second means comprising an intrinsically unbalanced bistable circuit having a node that intrinsically is in a high state at power-on coupled to said first node, and having a node that intrinsically is in a low state at power-on coupled to the input of said output buffer.
Claim 8
Dependent Claim
65 words
A device according to claim 5, wherein said intrinsically unbalanced bistable circuit comprises two cross-coupled inverting stages, a first stage comprising a pair of complementary, enhancement type transistors and having an output node coupled to said first node, a second stage comprising a pair of complementary transistors having a substantially unmodified threshold and having an output node coupled to the input of said output buffer.
Claim 9
Dependent Claim
43 words
A device according to claim 5, further comprising a pass transistor having a gate coupled to the supply node; and wherein the second current terminal of said at least one nonvolatile memory element is coupled to said first node through said pass transistor.
Claim 10
Dependent Claim
52 words
A device according to claim 6, wherein said nonvolatile memory element comprises a diffusion coinciding with the second current terminal thereof; wherein the two inverting stages comprise respective diffusions coinciding with the output nodes thereof; and wherein each of said diffusions have an incremented area to increase a relative junction capacitance thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-12 | 2002-04-13 | 2002-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-12 | 2006-04-13 | 2006-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-12 | 2010-04-13 | 2010-10-13 | $7700.00 | Window Closed / Lapsed |