US5821625A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Structure of chip on chip mounting preventing from crosstalk noise
Assignee: Panasonic Holdings Corp
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Filing: 1996-04-23
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Granted: 1998-10-13
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Expires: 2016-04-23
Abstract
Abstract The present invention reduces crosstalk, which occurs as a result of interference between signals running in each of respective wiring layers of a first semiconductor chip and a second semiconductor chip stacked surface to surface with a small gap. The semiconductor device includes a first semiconductor chip 1 having a first electrode pad 2 and a first wiring layer 9 in the main surface, and a second semiconductor chip 5 having a second electrode pad 6 and a second wiring layer 10 in the main surface confronting the first semiconductor chip. A bump 4 is provided for electrically coupling the first electrode pad 2 and the second electrode pad 6 together. An insulation layer 8 is disposed between the main surfaces of first semiconductor chip 1 and second semiconductor chip 5. An electro-conductive layer 7 is disposed between the main confronting surfaces of the first semiconductor chip and the second semiconductor chip.
Inventors
- 👤 Takayuki Yoshida
- 👤 Takashi Otsuka
- 👤 Hiroaki Fujimoto
- 👤 Tadaaki Mimura
- 👤 Ichiro Yamane
- 👤 Takio Yamashita
- 👤 Toshio Matsuki
- 👤 Yoshiaki Kasuga
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 23:17
CPC Classifications
H; H10; H10W; H10W78/00; H10W42/00; H10W42/20; H10W74/00; H10W74/01; H10W74/012; H10W74/10; H10W74/15; H10W90/00; H10W72/00; H10W72/01; H10W72/012; H10W72/01251; H10W72/01255; H10W72/071; H10W72/072; H10W72/073; H10W72/30; H10W72/351; H10W72/352; H10W72/353; H10W72/354; H10W72/851; H10W72/853; H10W72/856; H10W90/20; H10W90/22; H10W90/701; H10W90/721; H10W90/722; H10W90/724
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
196 words
A semiconductor device comprising: a first semiconductor chip having a wiring layer disposed in a first surface of said first semiconductor chip; a plurality of first electrode pads disposed on said first surface of said first semiconductor chip; a second semiconductor chip having a wiring layer disposed in a first surface of said second semiconductor chip, wherein said first surface of said first semiconductor chip confronts said first surface of said second semiconductor chip; a plurality of second electrode pads disposed on said first surface of said second semiconductor chip; a plurality of coupling members for electrically coupling said first electrode pads and said second electrode pads together; an insulation member disposed between said confronting first surfaces of said first semiconductor chip and said second semiconductor chip, wherein said insulation member comprises an insulation resin which fills a gap between said confronting surfaces of said first and second semiconductor chips so as to bond said chips together; and an electro-conductive member disposed between said confronting first surfaces of said first semiconductor chip and said second semiconductor chip so as to reduce crosstalk therebetween, wherein said electro-conductive member comprises an electro-conductive foil embedded in said insulation resin.
Claim 2
Dependent Claim
196 words
A semiconductor device comprising: a first semiconductor chip having a wiring layer disposed in a first surface of said first semiconductor chip; a plurality of first electrode pads disposed on said first surface of said first semiconductor chip; a second semiconductor chip having a wiring layer disposed in a first surface of said second semiconductor chip, wherein said first surface of said first semiconductor chip confronts said first surface of said second semiconductor chip; a plurality of second electrode pads disposed on said first surface of said second semiconductor chip; a plurality of coupling members for electrically coupling said first electrode pads and said second electrode pads together; an insulation member disposed between said confronting first surfaces of said first semiconductor chip and said second semiconductor chip, wherein said insulation member comprises an insulation resin which fills a gap between said confronting surfaces of said first and second semiconductor chips so as to bond said chips together; and an electro-conductive member disposed between said confronting first surfaces of said first semiconductor chip and said second semiconductor chip so as to reduce crosstalk therebetween, wherein said electro-conductive member comprises an electro-conductive foil embedded in said insulation resin.
Claim 3
Dependent Claim
151 words
A semiconductor device comprising: a first semiconductor chip having a first wiring layer and a first elements region in a first surface of said first semiconductor chip; a plurality of first electrode pads disposed on said first surface of said first semiconductor chip; a second semiconductor chip having a second wiring layer and a second elements region in a first surface of second semiconductor chip, wherein said first surface of said second semiconductor chip confronts said first surface of said first semiconductor chip; and a plurality of second electrode pads disposed on said first surface of said second semiconductor chip, said second electrode pads being positioned so as to correspond to said first electrode pads, wherein said first semiconductor chip is positioned relative to said second semiconductor chip so that wiring of said first wiring layer crosses wiring of said second wiring layer at a predetermined angle without having mutual contact.
Claim 4
Dependent Claim
151 words
A semiconductor device comprising: a first semiconductor chip having a first wiring layer and a first elements region in a first surface of said first semiconductor chip; a plurality of first electrode pads disposed on said first surface of said first semiconductor chip; a second semiconductor chip having a second wiring layer and a second elements region in a first surface of second semiconductor chip, wherein said first surface of said second semiconductor chip confronts said first surface of said first semiconductor chip; and a plurality of second electrode pads disposed on said first surface of said second semiconductor chip, said second electrode pads being positioned so as to correspond to said first electrode pads, wherein said first semiconductor chip is positioned relative to said second semiconductor chip so that wiring of said first wiring layer crosses wiring of said second wiring layer at a predetermined angle without having mutual contact.
Claim 5
Dependent Claim
162 words
A semiconductor device comprising: a first semiconductor chip having a first wiring layer and a first elements region in a first surface of said first semiconductor chip; a plurality of first electrode pads disposed on said first surface of said first semiconductor chip; a second semiconductor chip having a second wiring layer and a second elements region in a first surface of said second semiconductor chip, wherein said first surface of said second semiconductor chip confronts said first surface of said first semiconductor chip; and a plurality of second electrode pads disposed on said first surface of said second semiconductor chip, said second electrode pads being positioned so as to correspond to said first electrode pads, wherein a difference between a driving voltage of said first semiconductor chip and a driving voltage of said second semiconductor chip is smaller than a threshold voltage that determines ON and OFF of one said first and second semiconductor chips which has a lower driving voltage.
Claim 6
Dependent Claim
162 words
A semiconductor device comprising: a first semiconductor chip having a first wiring layer and a first elements region in a first surface of said first semiconductor chip; a plurality of first electrode pads disposed on said first surface of said first semiconductor chip; a second semiconductor chip having a second wiring layer and a second elements region in a first surface of said second semiconductor chip, wherein said first surface of said second semiconductor chip confronts said first surface of said first semiconductor chip; and a plurality of second electrode pads disposed on said first surface of said second semiconductor chip, said second electrode pads being positioned so as to correspond to said first electrode pads, wherein a difference between a driving voltage of said first semiconductor chip and a driving voltage of said second semiconductor chip is smaller than a threshold voltage that determines ON and OFF of one said first and second semiconductor chips which has a lower driving voltage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-12 | 2002-04-13 | 2002-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-12 | 2006-04-13 | 2006-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-12 | 2010-04-13 | 2010-10-13 | $7700.00 | Window Closed / Lapsed |