Abstract Methods and associated apparatus for simulating digital logic circuits with a general purpose computer system. A description of a digital logic circuit is converted into executable computer code. The code produced is capable of simulating the circuit's response to a large number of independent sets of circuit stimulus. The code is broken into separate modules which each simulate the circuit's operation during a particular clock phase. Loops within the code are limited in size to make efficient use of the computer's instruction cache and the data cache. Known constant nodes are propagated through the circuit before code is generated to eliminate the generation of unnecessary code. Code is only generated to simulate gates which may switch on a particular phase. Code which does not need to be evaluated during a particular phase is dropped. The circuit is broken into acyclic sets of gates and code is generated to iterate over each acyclic set of gates until stability is reached. A scoring function is used to prioritize which logic gate and which nodes are to be selected for code generation. Tri-state buffers are simulated using boolean operations. Drive-fight checking is also accomplished using boolean operations.
A computer operable method for increasing the efficiency of computer code generated by a circuit compiler for simulating, during a plurality of phases, the response of a synchronous digital logic circuit having at least one clock input, comprising the steps of: (a) dividing said circuit stimulus into a plurality of phases comprised of at least a first phase, wherein the state of said clock input is a constant value during each of said plurality of phases; (b) providing said circuit compiler with a net list which describes a digital logic circuit, said net list comprised of gates with outputs; (c) generating at least a first phase program which simulates the response of said digital logic circuit to said circuit stimulus during said first phase, wherein computer code is not generated for gates whose output values during said first phase cannot affect the response of said digital logic circuit during succeeding phases; (d) repeating step (c) for each of said plurality of phases.
Claim 2
Dependent Claim
162 words
A computer operable method for increasing the efficiency of computer code generated by a circuit compiler for simulating, during a plurality of phases, the response of a synchronous digital logic circuit having at least one clock input, comprising the steps of: (a) dividing said circuit stimulus into a plurality of phases comprised of at least a first phase, wherein the state of said clock input is a constant value during each of said plurality of phases; (b) providing said circuit compiler with a net list which describes a digital logic circuit, said net list comprised of gates with outputs; (c) generating at least a first phase program which simulates the response of said digital logic circuit to said circuit stimulus during said first phase, wherein computer code is not generated for gates whose output values during said first phase cannot affect the response of said digital logic circuit during succeeding phases; (d) repeating step (c) for each of said plurality of phases.
Claim 3
Dependent Claim
30 words
The method of claim 1, wherein step (c) further comprises generating an active set, said active set being a list of said gates which may switch during said first phase.
Claim 4
Dependent Claim
37 words
The method of claim 2, wherein said step (c) further comprises removing from said active set said gates whose output values during said first phase cannot affect the response of said digital logic circuit during succeeding phases.
Claim 5
Dependent Claim
23 words
The method of claim 3, wherein step (c) wherein computer code is only generated to simulate gates which are in said active set.