US5815032A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device capable of preventing fluctuations of substrate potential
Assignee: Mitsubishi Electric Corp
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Filing: 1996-08-12
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Granted: 1998-09-29
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Expires: 2016-08-12
Abstract
Abstract A detect circuit receives a write enable signal, a column address strobe signal and an output control signal to predetect a mode in which data is input from an input/output terminal. While a substrate potential generation circuit normally operates, a substrate potential holding circuit also operates when the detect circuit detects the mode in which data is input, so that biasing capability of a substrate potential generating portion is increased before the data is actually input from the input/output terminal.
Inventors
- 👤 Takuya Ariki
- 👤 Hiroshi Akamatsu
- 👤 Shigeru Mori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:53
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C5/00; G11C5/14; G11C5/145; G11C5/146; G11C11/4063; G11C11/407; G11C11/4074
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
82 words
A semiconductor integrated circuit inputting/outputting data in response to an internal signal, comprising: a semiconductor substrate; substrate voltage generating means for generating a predetermined potential to be supplied to said semiconductor substrate; detecting means for detecting a change in logic level of input data; and substrate potential holding means for generating a voltage to be supplied to said semiconductor substrate in response to detection of a change in said detecting means thereby to prevent fluctuation in the potential of said semiconductor substrate.
Claim 2
Dependent Claim
82 words
A semiconductor integrated circuit inputting/outputting data in response to an internal signal, comprising: a semiconductor substrate; substrate voltage generating means for generating a predetermined potential to be supplied to said semiconductor substrate; detecting means for detecting a change in logic level of input data; and substrate potential holding means for generating a voltage to be supplied to said semiconductor substrate in response to detection of a change in said detecting means thereby to prevent fluctuation in the potential of said semiconductor substrate.
Claim 3
Dependent Claim
24 words
The semiconductor integrated circuit according to claim 1, wherein said detecting means detects a predetermined logic level of an internal signal indicating data input.
Claim 4
Dependent Claim
60 words
The semiconductor integrated circuit according to claim 1, further comprising: an output buffer outputting data; and output controlling means for supplying an activated, output control signal to said output buffer, thereby controlling said output buffer to output the data, wherein said detecting means detects changes in logic level of said input data only when said output control signal is inactive.
Claim 5
Dependent Claim
23 words
The semiconductor integrated circuit according to claim 1, further comprising frequency dividing means for dividing the frequency of said change in logic level.
Claim 6
Dependent Claim
74 words
The semiconductor integrated circuit according to claim 2, further comprising: reference potential generating means for generating a reference potential to maintain the potential of said semiconductor substrate; and potential level comparing means for comparing the potential of said semiconductor substrate with said reference potential, said substrate potential holding means operates only when it is determined in said potential level comparing means that the potential of said semiconductor substrate is greater than said reference potential.
Claim 7
Dependent Claim
70 words
The semiconductor integrated circuit according to claim 1, further comprising: reference potential generating means for generating a reference potential to maintain the potential of said semiconductor substrate; and potential level comparing means for comparing the potential of said semiconductor substrate with said reference potential, said substrate potential holding means operates when said potential level comparing means determines that the potential of said semiconductor substrate is greater than said reference potential.
Claim 8
Dependent Claim
74 words
The semiconductor integrated circuit according to claim 3, further comprising: reference potential generating means for generating a reference potential to maintain the potential of said semiconductor substrate; and potential level comparing means for comparing the potential of said semiconductor substrate with said reference potential, said substrate potential holding means operates only when it is determined in said potential level comparing means that the potential of said semiconductor substrate is greater than said reference potential.
Claim 9
Dependent Claim
74 words
The semiconductor integrated circuit according to claim 4, further comprising: reference potential generating means for generating a reference potential to maintain the potential of said semiconductor substrate; and potential level comparing means for comparing the potential of said semiconductor substrate with said reference potential, said substrate potential holding means operates only when it is determined in said potential level comparing means that the potential of said semiconductor substrate is greater than said reference potential.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-28 | 2002-03-30 | 2002-09-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-28 | 2006-03-30 | 2006-09-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-28 | 2010-03-30 | 2010-09-29 | $7700.00 | Window Closed / Lapsed |