Power reduction circuits and systems for dynamic logic gates

Claim 2

A logic circuit, comprising: a first phase dynamic logic circuit comprising one or more dynamic logic stages; a second phase dynamic logic circuit comprising one or more dynamic logic stages; wherein each of said one or more dynamic logic stages comprises: a precharge node; a coupling device which when conducting couples said precharge node to a precharge voltage during a precharge phase; a discharge path connected to said precharge node which when conducting couples said precharge node to a voltage different than the precharge voltage during an evaluate phase; and an output for presenting a logic value responsive to a voltage at said precharge node; and further comprising control circuitry for controlling at least one of said dynamic logic stages as a storing stage such that said coupling device and said discharge path of said storing stage are concurrently not conducting during a predetermined time such that the logic value is maintained at said output; wherein the predetermined time is equal to or greater than a time period equal to said evaluate phase plus said precharge phase.

Claim 3

A logic circuit, comprising: a first chase dynamic logic circuit comprising one or more dynamic logic stages; a second chase dynamic logic circuit comprising one or more dynamic logic stages; wherein each of said one or more dynamic logic stages comprises: a precharge node; a coupling device which when conducting couples said precharge node to a precharge voltage during a precharge chase; a discharge path connected to said precharge node which when conducting couples said precharge node to a voltage different than the precharge voltage during an evaluate phase; and an output for presenting a logic value responsive to a voltage at said precharge node; and further comprising control circuitry for controlling at least one of said dynamic logic stages as a storing stage such that said coupling device and said discharge path of said storing stage are concurrently not conducting during a predetermined time such that the logic value is maintained at said output; wherein the predetermined time is equal to or greater than a time period equal to said evaluate phase plus said precharge phase; wherein said control circuitry is further for controlling all of said dynamic logic stages in addition to said storing stage; wherein said first phase dynamic logic circuit comprises said storing stage; and wherein said circuitry for controlling comprises: circuitry for generating a first clock signal occurring over clock cycles; circuitry for coupling the first clock signal to control said coupling device of each of said one or more dynamic logic stages of said first phase dynamic logic circuit other than said coupling device of said storing stage; circuitry for generating a second clock signal occurring over clock cycles; circuitry for coupling the second clock signal to control said coupling device of each of said one or more dynamic logic stages of said second phase dynamic logic circuit; and circuitry for coupling a signal complement of the second clock signal to control said coupling device of said storing stage.

Claim 4

A logic circuit, comprising: a first chase dynamic logic circuit comprising one or more dynamic logic stages; a second chase dynamic logic circuit comprising one or more dynamic logic stages; wherein each of said one or more dynamic logic stages comprises: a precharge node; a coupling device which when conducting couples said precharge node to a precharge voltage during a precharge chase; a discharge path connected to said precharge node which when conducting couples said precharge node to a voltage different than the precharge voltage during an evaluate phase; and an output for presenting a logic value responsive to a voltage at said precharge node; and further comprising control circuitry for controlling at least one of said dynamic logic stages as a storing stage such that said coupling device and said discharge path of said storing stage are concurrently not conducting during a predetermined time such that the logic value is maintained at said output; wherein the predetermined time is equal to or greater than a time period equal to said evaluate phase plus said precharge phase; wherein said control circuitry is further for controlling all of said dynamic logic stages in addition to said storing stage; wherein said first phase dynamic logic circuit comprises said storing stage; and wherein said circuitry for controlling comprises: circuitry for generating a first clock signal occurring over clock cycles; circuitry for coupling the first clock signal to control said coupling device of each of said one or more dynamic logic stages of said first phase dynamic logic circuit other than said coupling device of said storing stage; circuitry for generating a second clock signal occurring over clock cycles; circuitry for coupling the second clock signal to control said coupling device of each of said one or more dynamic logic stages of said second phase dynamic logic circuit; and circuitry for coupling a signal complement of the second clock signal to control said coupling device of said storing stage.

Claim 5

The logic circuit of claim 2: wherein said discharge path comprises a discharge transistor coupled to receive a clock signal at its gate; and wherein said control circuitry further comprises: circuitry for coupling the first clock signal to said discharge transistor in said discharge path of each of said one or more dynamic logic stages of said first phase dynamic logic circuit; and circuitry for coupling the second clock signal to said discharge transistor in said discharge path of each of said one or more dynamic logic stages of said second phase dynamic logic circuit.

Claim 6

The logic circuit of claim 3: wherein, during a time immediately preceding the predetermined time: the first clock is disabling to said coupling device of each of said one or more dynamic logic stages of said first phase dynamic logic circuit other than said coupling device of said storing stage; and the first clock is enabling to said discharge transistor in said discharge path of each of said one or more dynamic logic stages in said first phase dynamic logic circuit.

Claim 7

The logic circuit of claim 3: wherein, during a time immediately preceding the predetermined time: the second clock is disabling to said discharge transistor in said discharge path of each of said one or more dynamic logic stages of said second phase dynamic logic circuit; the signal complement of the second clock signal is disabling to said coupling device of said storing stage; and the second clock is enabling to said coupling device of each of said one or more dynamic logic stages of said second phase dynamic logic circuit.

Claim 8

The logic circuit of claim 3: wherein, during a time immediately preceding the predetermined time: the first clock is disabling to said coupling device of each of said one or more dynamic logic stages of said first phase dynamic logic circuit other than said coupling device of said storing stage; the first clock is enabling to said discharge transistor in said discharge path of each of said one or more dynamic logic stages in said first phase dynamic logic circuit; the second clock is disabling to said discharge transistor in said discharge path of each of said one or more dynamic logic stages of said second phase dynamic logic circuit; the signal complement of the second clock signal is disabling to said coupling device of said storing stage; and the second clock is enabling to said coupling device of each of said one or more dynamic logic stages of said second phase dynamic logic circuit.

Claim 9

The logic circuit of claim 3: wherein, during a time immediately after the predetermined time: the first clock is enabling to said coupling device of each of said one or more dynamic logic stages of said first phase dynamic logic circuit other than said coupling device of said storing stage; and the first clock is disabling to said discharge transistor in said discharge path of each of said one or more dynamic logic stages in said first phase dynamic logic circuit.

Claim 10

The logic circuit of claim 3: wherein, during a time immediately after the predetermined time: the second clock is enabling to said discharge device of each of said one or more dynamic logic stages of said second phase dynamic logic circuit; the second clock is disabling to said coupling device of each of said one or more dynamic logic stages of said second phase dynamic logic circuit; and the signal complement of the second clock is enabling to said coupling device of said storing stage.

Claim 11

The logic circuit of claim 3: wherein, during a time immediately after the predetermined time: the first clock is enabling to said coupling device of each of said one or more dynamic logic stages of said first phase dynamic logic circuit other than said coupling device of said storing stage; the first clock is disabling to said discharge transistor in said discharge path of each of said one or more dynamic logic stages in said first phase dynamic logic circuit; the second clock is enabling to said discharge device of each of said one or more dynamic logic stages of said second phase dynamic logic circuit; the second clock is disabling to said coupling device of each of said one or more dynamic logic stages of said second phase dynamic logic circuit; and the signal complement of the second clock is enabling to said coupling device of said storing stage.

Claim 12

The logic circuit of claim 3: wherein, during a time immediately preceding the predetermined time: the first clock is enabling to said coupling device of each of said one or more dynamic logic stages of said first phase dynamic logic circuit other than said coupling device of said storing stage; the first clock is disabling to said discharge transistor in said discharge path of each of said one or more dynamic logic stages in said first phase dynamic logic circuit; the second clock is disabling to said discharge transistor in said discharge path of each of said one or more dynamic logic stages of said second phase dynamic logic circuit; the signal complement of the second clock signal is disabling to said coupling device of said storing stage; and the second clock is enabling to said coupling device of each of said one or more dynamic logic stages of said second phase dynamic logic circuit; and wherein, during a time immediately after the predetermined time: the first clock is enabling to said coupling device of each of said one or more dynamic logic stages of said first phase dynamic logic circuit other than said coupling device of said storing stage; the first clock is disabling to said discharge transistor in said discharge path of each of said one or more dynamic logic stages in said first phase dynamic logic circuit; the second clock is enabling to said discharge device of each of said one or more dynamic logic stages of said second phase dynamic logic circuit; the second clock is disabling to said coupling device of each of said one or more dynamic logic stages of said second phase dynamic logic circuit; and the signal complement of the second clock is enabling to said coupling device of said storing stage.

Claim 13

The logic circuit of claim 1: wherein said one or more dynamic logic stages of said first phase dynamic logic circuit comprises a first cascade signal path having a plurality of stages including a first stage and a last stage; wherein said first phase dynamic logic circuit comprises said storing stage; and wherein said storing stage is the last stage of said first signal path.

Claim 14

The logic circuit of claim 1: wherein said one or more dynamic logic stages of said first phase dynamic logic circuit comprises a first cascade signal path having a plurality of stages including a first stage and a last stage; wherein said one or more dynamic logic stages of said second phase dynamic logic circuit comprises a second signal path having a first stage and a last stage; wherein said first phase dynamic logic circuit comprises said storing stage; and wherein said storing stage is a stage other than the last stage of said first signal path.

Claim 15

A logic circuit, comprising: a first phase dynamic logic circuit comprising one or more dynamic logic stages; a second phase dynamic logic circuit comprising one or more dynamic logic stages; wherein each of said one or more dynamic logic stages comprises: a precharge node; a coupling device which when conducting couples said precharge node to a precharge voltage during a precharge phase; a discharge path connected to said precharge node which when conducting couples said precharge node to a voltage different than the precharge voltage during an evaluate chase; and an output for presenting a logic value responsive to a voltage at said precharge node; and further comprising control circuitry for controlling at least one of said dynamic logic stages as a storing stage such that said coupling device and said discharge path of said storing stage are concurrently not conducting during a predetermined time such that the logic value is maintained at said output; wherein the predetermined time is equal to or greater than a time period equal to said evaluate phase plus said precharge phase; wherein said one or more dynamic logic stages of said first phase dynamic logic circuit comprises a first signal path having a first stage and a last stage; wherein said one or more dynamic logic stages of said second phase dynamic logic circuit comprises a second signal path having a first stage and a last stage; wherein said first phase dynamic logic circuit comprises said storing stage; wherein said storing stage is a stage other than the last stage of said first signal path; wherein said control circuitry is further for controlling all of said dynamic logic stages in addition to said storing stage; and wherein said control circuitry further comprises: circuitry for generating a first clock signal; circuitry for generating a second clock signal; circuitry for coupling the first clock signal to control said coupling device of each of said one or more dynamic logic stages of said first signal path and prior to said storing stage; circuitry for coupling the second clock signal to control said coupling device of each of said one or more dynamic logic stages of said second signal path; and circuitry for coupling a signal complement of the second clock signal to control said coupling device of said storing stage.

Claim 16

A logic circuit, comprising: a first phase dynamic logic circuit comprising one or more dynamic logic stages; a second phase dynamic logic circuit comprising one or more dynamic logic stages; wherein each of said one or more dynamic logic stages comprises: a precharge node; a coupling device which when conducting couples said precharge node to a precharge voltage during a precharge phase; a discharge path connected to said precharge node which when conducting couples said precharge node to a voltage different than the precharge voltage during an evaluate chase; and an output for presenting a logic value responsive to a voltage at said precharge node; and further comprising control circuitry for controlling at least one of said dynamic logic stages as a storing stage such that said coupling device and said discharge path of said storing stage are concurrently not conducting during a predetermined time such that the logic value is maintained at said output; wherein the predetermined time is equal to or greater than a time period equal to said evaluate phase plus said precharge phase; wherein said one or more dynamic logic stages of said first phase dynamic logic circuit comprises a first signal path having a first stage and a last stage; wherein said one or more dynamic logic stages of said second phase dynamic logic circuit comprises a second signal path having a first stage and a last stage; wherein said first phase dynamic logic circuit comprises said storing stage; wherein said storing stage is a stage other than the last stage of said first signal path; wherein said control circuitry is further for controlling all of said dynamic logic stages in addition to said storing stage; and wherein said control circuitry further comprises: circuitry for generating a first clock signal; circuitry for generating a second clock signal; circuitry for coupling the first clock signal to control said coupling device of each of said one or more dynamic logic stages of said first signal path and prior to said storing stage; circuitry for coupling the second clock signal to control said coupling device of each of said one or more dynamic logic stages of said second signal path; and circuitry for coupling a signal complement of the second clock signal to control said coupling device of said storing stage.

Claim 17

The logic circuit of claim 13: wherein said discharge path comprises a discharge transistor coupled to receive a clock signal at its gate; and wherein said control circuitry further comprises: circuitry for generating a third clock signal; circuitry for coupling the first clock signal to control said discharge transistor in said discharge path of each of said one or more dynamic logic stages in said first signal path and which is prior to and including said storing stage; circuitry for coupling the third clock signal to control said coupling device and said discharge transistor of each of said one or more dynamic logic stages in said first signal path and which is after said storing stage; and circuitry for coupling the second clock signal to said discharge transistor in each of said one or more dynamic logic stages of said second phase dynamic logic circuit.

Claim 18

The logic circuit of claim 14: wherein, during a time immediately preceding the predetermined time: the first clock is disabling to said coupling device of each of said one or more dynamic logic stages of said first signal path and prior to said storing stage; and the first clock is enabling to said discharge transistor in said discharge path of each of said one or more dynamic logic stages in said first signal path and which is prior to and including said storing stage.

Claim 19

The logic circuit of claim 14: wherein, during a time immediately preceding the predetermined time: the second clock is enabling to said coupling device of each of said one or more dynamic logic stages of said second phase dynamic logic circuit; the second clock is disabling to said discharge transistor in each of said one or more dynamic logic stages of said second phase dynamic logic circuit; a complement of the second clock is disabling to said coupling device of said storing stage.

Claim 20

The logic circuit of claim 14: wherein, during a time immediately preceding the predetermined time the third clock is enabling to said coupling device and disabling to said discharge transistor of each of said one or more dynamic logic stages in said first signal path and which is after said storing stage.

Claim 21

The logic circuit of claim 14: wherein, during a time immediately preceding the predetermined time: the first clock is disabling to said coupling device of each of said one or more dynamic logic stages of said first signal path and prior to said storing stage; the first clock is enabling to said discharge transistor in said discharge path of each of said one or more dynamic logic stages in said first signal path and which is prior to and including said storing stage; the second clock is enabling to said coupling device of each of said one or more dynamic logic stages of said second phase dynamic logic circuit; the second clock is disabling to said discharge transistor in each of said one or more dynamic logic stages of said second phase dynamic logic circuit; a complement of the second clock is disabling to said coupling device of said storing stage; and the third clock is enabling to said coupling device and disabling to said discharge transistor of each of said one or more dynamic logic stages in said first signal path and which is after said storing stage.

Claim 22

The logic circuit of claim 14: wherein, during a time immediately after the predetermined time: the first clock is enabling to said coupling device of each of said one or more dynamic logic stages of said first signal path and prior to said storing stage; and the first clock is disabling to said discharge transistor in said discharge path of each of said one or more dynamic logic stages in said first signal path which is prior to and including said storing stage.

Claim 23

The logic circuit of claim 14: wherein, during a time immediately after the predetermined time: the second clock is enabling to said coupling device of each of said one or more dynamic logic stages of said second signal path; the second clock is disabling to said discharge transistor in each of said one or more dynamic logic stages of said second phase dynamic logic circuit; and a complement of the second clock is disabling to said coupling device of said storing stage.

Claim 24

The logic circuit of claim 14: wherein, during a time immediately after the predetermined time the third clock is disabling to said coupling device and enabling to said discharge transistor of each of said one or more dynamic logic stages in said first signal path after said storing stage.

Claim 25

The logic circuit of claim 14: wherein, during a time immediately after the predetermined time: the first clock is enabling to said coupling device of each of said one or more dynamic logic stages of said first signal path and prior to said storing stage; the first clock is disabling to said discharge transistor in said discharge path of each of said one or more dynamic logic stages in said first signal path which is prior to and including said storing stage; the second clock is enabling to said coupling device of each of said one or more dynamic logic stages of said second signal path; the second clock is disabling to said discharge transistor in each of said one or more dynamic logic stages of said second phase dynamic logic circuit; a complement of the second clock is disabling to said coupling device of said storing stage; and the third clock is disabling to said coupling device and enabling to said discharge transistor of each of said one or more dynamic logic stages in said first signal path after said storing stage.

Claim 26

The logic circuit of claim 14: wherein, during a time immediately preceding the predetermined time: the first clock is disabling to said coupling device of each of said one or more dynamic logic stages of said first signal path and prior to said storing stage; the first clock is enabling to said discharge transistor in said discharge path of each of said one or more dynamic logic stages in said first signal path and which is prior to and including said storing stage; the second clock is enabling to said coupling device of each of said one or more dynamic logic stages of said second phase dynamic logic circuit; the second clock is disabling to said discharge transistor in each of said one or more dynamic logic stages of said second phase dynamic logic circuit; a complement of the second clock is disabling to said coupling device of said storing stage; and the third clock is disabling to said coupling device and enabling to said discharge transistor of each of said one or more dynamic logic stages in said first signal path and which is after said storing stage.

Claim 27

The logic circuit of claim 14: wherein, during a time immediately after the predetermined time: the first clock is disabling to said coupling device of each of said one or more dynamic logic stages of said first signal path and prior to said storing stage; the first clock is enabling to said discharge transistor in said discharge path of each of said one or more dynamic logic stages in said first signal path which is prior to and including said storing stage; the second clock is enabling to said coupling device of each of said one or more dynamic logic stages of said second signal path; the second clock is disabling to said discharge transistor in each of said one or more dynamic logic stages of said second phase dynamic logic circuit; a complement of the second clock is disabling to said coupling device of said storing stage; and the third clock is disabling to said coupling device and enabling to said discharge transistor of each of said one or more dynamic logic stages in said first signal path after said storing stage.

Claim 28

The logic circuit of claim 24 wherein said discharge path of said storing stage comprises a logic transistor for receiving an input signal, and wherein said input signal is disabling during the predetermined time.

Claim 29

A logic circuit comprising: a source of a first clock signal having alternating precharge phases and evaluate phases; a source of a second clock signal having alternating precharge phases and evaluate phases in an opposite phase to said first clock signal; a first phase dynamic logic circuit comprising at least one first phase dynamic logic stage disposed in cascade with a first phase storage dynamic logic stage, each first phase dynamic logic stage including a precharge node, a coupling device which when conducting couples said precharge node to a precharge voltage during said precharge phase of said first clock signal, a discharge path connected to said precharge node which when conducting couples said precharge node to a voltage different than the precharge voltage during said evaluate phase of said first clock signal, and an output for presenting a logic value responsive to a voltage at said precharge node, and wherein said first phase storage dynamic logic stage including a precharge node, an invertor having an input receiving said second clock signal; a coupling device which when conducting couples said precharge node to a precharge voltage, said coupling device connected to said invertor to be conducting during said evaluate phase of said second clock signal, a discharge path connected to said precharge node which when conducting couples said precharge node to a voltage different than the precharge voltage during said evaluate phase of said first clock signal, and an output for presenting a logic value responsive to a voltage at said precharge node, a second phase dynamic logic circuit comprising a plurality of second phase dynamic logic stages disposed in cascade, each second phase dynamic logic stage including a precharge node, a coupling device which when conducting couples said precharge node to a precharge voltage during said precharge phase of said second clock signal, a discharge path connected to said precharge node which when conducting couples said precharge node to a voltage different than the precharge voltage during said evaluate phase of said second clock signal, and an output for presenting a logic value responsive to a voltage at said precharge node; whereby both said first clock signal and said second clock signal can be held at said precharge phase for at time longer than the sum of said precharge phase and said evaluate phase of said first clock signal with said first phase storage dynamic logic stage retaining a state corresponding to whether said discharge path was conducting or nonconducting during the immediate prior evaluate phase of said first clock signal.

Claim 30

A logic circuit comprising: a source of a first clock signal having alternating precharge phases and evaluate phases; a source of a second clock signal having alternating precharge phases and evaluate phases in an opposite phase to said first clock signal; a first phase dynamic logic circuit comprising at least one first phase dynamic logic stage disposed in cascade with a first phase storage dynamic logic stage, each first phase dynamic logic stage including a precharge node, a coupling device which when conducting couples said precharge node to a precharge voltage during said precharge phase of said first clock signal, a discharge path connected to said precharge node which when conducting couples said precharge node to a voltage different than the precharge voltage during said evaluate phase of said first clock signal, and an output for presenting a logic value responsive to a voltage at said precharge node, and wherein said first phase storage dynamic logic stage including a precharge node, an invertor having an input receiving said second clock signal; a coupling device which when conducting couples said precharge node to a precharge voltage, said coupling device connected to said invertor to be conducting during said evaluate phase of said second clock signal, a discharge path connected to said precharge node which when conducting couples said precharge node to a voltage different than the precharge voltage during said evaluate phase of said first clock signal, and an output for presenting a logic value responsive to a voltage at said precharge node, a second phase dynamic logic circuit comprising a plurality of second phase dynamic logic stages disposed in cascade, each second phase dynamic logic stage including a precharge node, a coupling device which when conducting couples said precharge node to a precharge voltage during said precharge phase of said second clock signal, a discharge path connected to said precharge node which when conducting couples said precharge node to a voltage different than the precharge voltage during said evaluate phase of said second clock signal, and an output for presenting a logic value responsive to a voltage at said precharge node; whereby both said first clock signal and said second clock signal can be held at said precharge phase for at time longer than the sum of said precharge phase and said evaluate phase of said first clock signal with said first phase storage dynamic logic stage retaining a state corresponding to whether said discharge path was conducting or nonconducting during the immediate prior evaluate phase of said first clock signal.

Claim 31

A logic circuit comprising: a source of a first clock signal having alternating precharge phases and evaluate phases; a source of a second clock signal having alternating precharge phases and evaluate phases in an opposite phase to said first clock signal; a source of a third clock signal having alternating precharge and evaluate phases generally in the same phase as said first clock signal; a first phase dynamic logic circuit comprising a plurality of first phase dynamic logic stages disposed in cascade with a first phase storage dynamic logic stage, each dynamic logic stage including a precharge node, an invertor having an input receiving said second clock signal; a coupling device which when conducting couples said precharge node to a precharge voltage, said first phase dynamic logic stages disposed prior to said first phase storage dynamic logic state receiving said first clock signal and conducting during said precharge phase of said first clock signal, said first phase storage dynamic logic state connected to said inverter and conducting during said evaluate phase of said second clock signal and said first phase dynamic logic states disposed following said first phase storage dynamic logic state receiving said third clock signal and conducting during said precharge phase of said third clock signal, a discharge path connected to said precharge node which when conducting couples said precharge node to a voltage different than the precharge voltage, said first phase dynamic logic stages disposed prior to said first phase storage dynamic logic state and said first phase storage dynamic logic stage receiving said first clock signal and conducting during said evaluate phase of said first clock signal, and said first phase dynamic logic states disposed following said first phase storage dynamic logic state receiving said third clock signal and conducting during said precharge phase of said third clock signal, and an output for presenting a logic value responsive to a voltage at said precharge node, a second phase dynamic logic circuit comprising a plurality of second phase dynamic logic stages disposed in cascade, each second phase dynamic logic stage including a precharge node, a coupling device which when conducting couples said precharge node to a precharge voltage during said precharge phase of said second clock signal, a discharge path connected to said precharge node which when conducting couples said precharge node to a voltage different than the precharge voltage during said evaluate phase of said second clock signal, and an output for presenting a logic value responsive to a voltage at said precharge node; whereby upon omitting said evaluate phase of said third clock signal and thereafter holding said first clock signal, said second clock signal and said third clock signal at said precharge phase with said first phase storage dynamic logic stage retaining a state corresponding to whether said discharge path was conducting or nonconducting during the immediate prior evaluate phase of said first clock.

Claim 32

A logic circuit comprising: a source of a first clock signal having alternating precharge phases and evaluate phases; a source of a second clock signal having alternating precharge phases and evaluate phases in an opposite phase to said first clock signal; a source of a third clock signal having alternating precharge and evaluate phases generally in the same phase as said first clock signal; a first phase dynamic logic circuit comprising a plurality of first phase dynamic logic stages disposed in cascade with a first phase storage dynamic logic stage, each dynamic logic stage including a precharge node, an invertor having an input receiving said second clock signal; a coupling device which when conducting couples said precharge node to a precharge voltage, said first phase dynamic logic stages disposed prior to said first phase storage dynamic logic state receiving said first clock signal and conducting during said precharge phase of said first clock signal, said first phase storage dynamic logic state connected to said inverter and conducting during said evaluate phase of said second clock signal and said first phase dynamic logic states disposed following said first phase storage dynamic logic state receiving said third clock signal and conducting during said precharge phase of said third clock signal, a discharge path connected to said precharge node which when conducting couples said precharge node to a voltage different than the precharge voltage, said first phase dynamic logic stages disposed prior to said first phase storage dynamic logic state and said first phase storage dynamic logic stage receiving said first clock signal and conducting during said evaluate phase of said first clock signal, and said first phase dynamic logic states disposed following said first phase storage dynamic logic state receiving said third clock signal and conducting during said precharge phase of said third clock signal, and an output for presenting a logic value responsive to a voltage at said precharge node, a second phase dynamic logic circuit comprising a plurality of second phase dynamic logic stages disposed in cascade, each second phase dynamic logic stage including a precharge node, a coupling device which when conducting couples said precharge node to a precharge voltage during said precharge phase of said second clock signal, a discharge path connected to said precharge node which when conducting couples said precharge node to a voltage different than the precharge voltage during said evaluate phase of said second clock signal, and an output for presenting a logic value responsive to a voltage at said precharge node; whereby upon omitting said evaluate phase of said third clock signal and thereafter holding said first clock signal, said second clock signal and said third clock signal at said precharge phase with said first phase storage dynamic logic stage retaining a state corresponding to whether said discharge path was conducting or nonconducting during the immediate prior evaluate phase of said first clock.