Current-mirror-biased pre-charged logic circuit

Claim 2

A dynamic logic curicut comprising at least one dynamic logic cell and a bias circuit, each dynamic logic cell comprising a first field-effect transistor having a channel extending between a first supply voltage and a pre-charged node of a respective logic network and also comprising a second field-effect transistor having a channel extending between a second supply voltage and the respective logic network, the gate of each of the first and second transistors being connected to a clocked input signal, the bias circuit comprising a third field-effect transistor for each dynamic logic cell and also comprising a fouth field-effect transistor in each dynamic logic cell extending between the first supply voltage and the pre-charged node of the respective logic network, the gate of each of the third transistors being connected to the gate of the fourth transistor, the channel of the fourth transistor extending between the first supply voltage and an intermediate node, the resistance element extending between the intermediate node and the second supply voltage, the gate of the fourth transistor being connected to the intermediate node, whereby all of the transistors and the resistance element are formed as an integral part of an integrated logic circuit, and whereby current flows from the first supply voltage to the pre charged nodes of the logic networks at a steady rate determined by the relative dimensions selected for each of the third transistors and the fourth transistor and by the resistance value selected for the resistance element.

Claim 3

A dynamic logic circuit as in claim 1, wherein each of the first and third transistors and the fourth transistor are p-channel transistors, wherein each of the second transistors are n-channel transistors, and wherein the first supply voltage is more positive than the second supply voltage.

Claim 4

A dynamic logic circuit as in claim 1, wherein each of the first and third transistors and the fourth transistor are n-channel transistors, wherein each of the second transistors are p-channel transistors, and wherein the first supply voltage is more negative than the second supply voltage.

Claim 5

A dynamic logic circuit as in claim 1, wherein the resistance element comprises a resistor.

Claim 6

A dynamic logic circuit as in claim 1, wherein the resistance element comprises a diode.

Claim 7

A dynamic logic circuit as in claim 2, wherein the resistance element comprises a fifth and a sixth field-effect transistors having their channels connected serially, the gate of each of the fifth and sixth transistors being connected together and to the connection point between the channels of those transistors, the fifth transistor being a p-channel transistor and the sixth transistor being a n-channel transistor.

Claim 8

A dynamic logic circuit as in claim 3, wherein the resistance element comprises a fifth and a sixth field-effect transistors having their channels connected serially, the gate of each of the fifth and sixth transistros being connected together and to the connection point between the channels of those transistors, the fifth transistor being a n-channel transistor and the sixth transistor being a p-channel transistor.

Claim 9

A dynamic logic circuit comprising at least one of a first type of dynamic logic cell and at least one of a second type of dynamic logic cell, and also comprising a bias circuit, each of the first type of dynamic logic cells comprising a first field-effect transistor having a channel extending between a first supply voltage and a pre-charged node of a respective logic network and also comprising a second field-effect transistor having a channel extending between a second supply voltage and the respective logic network, the gate of each of the first and second transistors being connected to a first clocked input signal each of the second type of dynamic logic cells comprising a field-effect third transistor having a channel extending between the second supply voltage and a pre-charged node of a respective logic network and also comprising a fourth field-effect transistor having a channel extending between the first supply voltage and the respective logic network, the gate of each of the third and fourth transistors being connected to a second clocked input signal, the bias circuit comprising a fifth field-effect transistor for each of the first type of dynamic logic cells and comprising a sixth field-effect transistor for each of the second type of dynamic logic cells, the channel of the fifth transistor in each first type of dynamic logic cell extending between the first supply voltage and the pre-charged node of the respective logic notwork, the channel of the sixth transistor in each second type of dynamic logic cell extending between the second supply voltage and the pre-charged node of the respective logic network, the bias circuit also comprising seventh and eighth field-effect transistors and a resistance element, the channel of the seventh transistor being connected between the first supply voltage and a first intermediate node, the channel of the eighth transistor being connected between the second supply voltage and a second intermediate node, the resistance element extending between the first and second intermediate nodes, the gate of each of the fifth transistors being connected to the gate of the seventh transistor and to the first intermediate node, the gate of each of the sixth transistors being connected to the gate of the eighth transistor and to the second intermediate node, whereby all of the transistors and the resistance element are formed as an integral part of an integrated logic circuit, whereby current flows from the first supply voltage to the pre-charged nodes of the logic networks of the first type of logic cells at a steady rate determined by the resistance value selected for the resistance element and by the relative dimensions selected for each of the fifth transistors and the seventh transistor, and whereby current flows from the second supply voltage to the pre-charged nodes of the logic networks of the second type of logic cells at a steady rate determined by the resistance value selected for the resistance element and by the relative dimensions selected for each of the sixth transistors and the eighth transistor.

Claim 10

A dynamic logic circuit comprising at least one of a first type of dynamic logic cell and at least one of a second type of dynamic logic cell, and also comprising a bias circuit, each of the first type of dynamic logic cells comprising a first field-effect transistor having a channel extending between a first supply voltage and a pre-charged node of a respective logic network and also comprising a second field-effect transistor having a channel extending between a second supply voltage and the respective logic network, the gate of each of the first and second transistors being connected to a first clocked input signal each of the second type of dynamic logic cells comprising a field-effect third transistor having a channel extending between the second supply voltage and a pre-charged node of a respective logic network and also comprising a fourth field-effect transistor having a channel extending between the first supply voltage and the respective logic network, the gate of each of the third and fourth transistors being connected to a second clocked input signal, the bias circuit comprising a fifth field-effect transistor for each of the first type of dynamic logic cells and comprising a sixth field-effect transistor for each of the second type of dynamic logic cells, the channel of the fifth transistor in each first type of dynamic logic cell extending between the first supply voltage and the pre-charged node of the respective logic notwork, the channel of the sixth transistor in each second type of dynamic logic cell extending between the second supply voltage and the pre-charged node of the respective logic network, the bias circuit also comprising seventh and eighth field-effect transistors and a resistance element, the channel of the seventh transistor being connected between the first supply voltage and a first intermediate node, the channel of the eighth transistor being connected between the second supply voltage and a second intermediate node, the resistance element extending between the first and second intermediate nodes, the gate of each of the fifth transistors being connected to the gate of the seventh transistor and to the first intermediate node, the gate of each of the sixth transistors being connected to the gate of the eighth transistor and to the second intermediate node, whereby all of the transistors and the resistance element are formed as an integral part of an integrated logic circuit, whereby current flows from the first supply voltage to the pre-charged nodes of the logic networks of the first type of logic cells at a steady rate determined by the resistance value selected for the resistance element and by the relative dimensions selected for each of the fifth transistors and the seventh transistor, and whereby current flows from the second supply voltage to the pre-charged nodes of the logic networks of the second type of logic cells at a steady rate determined by the resistance value selected for the resistance element and by the relative dimensions selected for each of the sixth transistors and the eighth transistor.