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US5812708A
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Method and apparatus for distributing an optical clock in an integrated circuit
Assignee: Intel Corp
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Filing: 1996-12-31
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Granted: 1998-09-22
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Expires: 2016-12-31
Abstract
Abstract A method and an apparatus for optically clocking an integrated circuit in a semiconductor. In one embodiment, a laser is configured to emit infrared laser pulses at a desired clock frequency. The laser pulses are separated into a plurality of split laser pulses, each of which are focused through the back side of a C4 packaged integrated circuit die into P-N junctions distributed throughout the integrated circuit die. Each P-N junction locally generates a photocurrent in response to the split laser beams. Each of the photocurrents are locally converted into voltages and thus into local clock signals, which are used to clock the local area of the integrated circuit. With the presently described optical clocking technique, the local clock signals have extremely low clock skew. The presently described technique may be employed in integrated circuits system-wide, in multi-chip modules, or in an individual integrated circuit. By removing the global clock distribution network from the silicon, the present invention allows chip area used in the prior art for a global clock distribution networks to be used instead for signal routing or allows overall die sizes to be reduced.
Inventors
- 👤 Vallur R. Rao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:59
CPC Classifications
G; G02; G02B; G02B6/00; G02B6/24; G02B6/42; G02B6/43; G06; G06F; G06F1/00; G06F1/04; G06F1/10; G06F1/105
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
89 words
An optical clock distribution network, comprising: a first P-N junction disposed in a first semiconductor including at least a front and back side; a master laser configured to emit master laser pulses at a master clock frequency through the back side of the first semiconductor into the first P-N junction; and a first current to voltage converter coupled to the first P-N junction, the first current to voltage converter generating a first clock signal configured to clock a first area of an integrated circuit disposed in the first semiconductor.
Claim 2
Dependent Claim
89 words
An optical clock distribution network, comprising: a first P-N junction disposed in a first semiconductor including at least a front and back side; a master laser configured to emit master laser pulses at a master clock frequency through the back side of the first semiconductor into the first P-N junction; and a first current to voltage converter coupled to the first P-N junction, the first current to voltage converter generating a first clock signal configured to clock a first area of an integrated circuit disposed in the first semiconductor.
Claim 3
Dependent Claim
30 words
The optical clock distribution network described in claim 1 further comprising a first buffer coupled between the first current to voltage converter and the first area of the integrated circuit.
Claim 4
Dependent Claim
117 words
The optical clock distribution network described in claim 1 further comprising: a second P-N junction in the first semiconductor; an optics element coupled between the master laser and the first and second P-N junctions, the optics element configured to split the master laser pulses into first and second split laser pulses focused through the back side of the first semiconductor into the first and second P-N junctions respectively; and a second current to voltage converter coupled to the second P-N junction, the second current to voltage converter generating a second clock signal configured to clock a second area of the integrated circuit in the first semiconductor, the first and second clock signals having the master clock frequency.
Claim 5
Dependent Claim
138 words
The optical clock distribution network described in claim 1 further comprising: a second P-N junction in a second semiconductor; an optics element coupled between the master laser and the first and second P-N junctions, the optics element configured to split the master laser pulses into first and second split laser pulses, the first split laser pulses focused through the back side of the first semiconductor into the first P-N junction, the second split laser pulses focused through a back side of the second semiconductor into the second P-N junction; and a second current to voltage converter coupled to the second P-N junction, the second current to voltage converter generating a second clock signal configured to clock a second area of an integrated circuit in the second semiconductor, the first and second clock signals having the master clock frequency.
Claim 6
Dependent Claim
52 words
The optical clock distribution network described in claim 1 wherein the first semiconductor includes portions that define a recess disposed between the master laser and the first P-N junction, the recess increasing a transmission of the master laser pulses through the back side of the first semiconductor into the first P-N junction.
Claim 7
Dependent Claim
36 words
The optical clock distribution network described in claim 3 wherein the optics element is configured to split the first and second split laser pulses with substantially no skew between the first and second split laser pulses.
Claim 8
Dependent Claim
39 words
The optical clock distribution network described in claim 3 wherein the optics element comprises a first micro lens configured to focus the first split laser pulses and a second micro lens configured to focus the second split laser pulses.
Claim 9
Dependent Claim
37 words
The optical clock distribution network described in claim 3 wherein the optics element comprises a first waveguide configured to focus the first split laser pulses and a second waveguide configured to focus the second split laser pulses.
Claim 10
Dependent Claim
26 words
The optical clock distribution network described in claim 3 wherein the optics element comprises a hologram configured to generate the first and second split laser pulses.
Claim 11
Dependent Claim
22 words
The optical clock distribution network described in claim 8 wherein the hologram is etched into the back side of the first semiconductor.
Claim 12
Dependent Claim
22 words
The optical clock distribution network described in claim 1 wherein the master laser operates at a wavelength approximately equal to 1.054 μm.
Claim 13
Dependent Claim
22 words
The optical clock distribution network described in claim 1 wherein the master laser operates at a wavelength approximately equal to 1.06 μm.
Claim 14
Dependent Claim
24 words
The optical clock distribution network described in claim 5 wherein the master laser operates at a wavelength approximately equal to 0.4 to 0.7 μm.
Claim 15
Dependent Claim
24 words
The optical clock distribution network described in claim 5 wherein the master laser operates at a wavelength approximately equal to 0.7 to 1.0 μm.
Claim 16
Dependent Claim
21 words
The optical clock distribution network described in claim 14 wherein the recess is back filled with a visible light transparent material.
Claim 17
Dependent Claim
18 words
The optical clock distribution network described in claim 1 wherein the master laser is a mode locked laser.
Claim 18
Dependent Claim
17 words
The optical clock distribution network described in claim 1 wherein the master laser is a modulated laser.
Claim 19
Dependent Claim
15 words
The optical clock distribution network described in claim 1 wherein the first semiconductor comprises silicon.
Claim 20
Dependent Claim
21 words
The optical clock distribution network described in claim 4 wherein the first and second semiconductors are comprised in a multi-chip module.
Claim 21
Dependent Claim
21 words
The optical clock distribution network described in claim 4 wherein the first and second semiconductors are comprised in a computer system.
Claim 22
Independent Claim
94 words
A method for optically clocking an integrated circuit in a semiconductor including at least a front and back side, the method comprising the steps of: operating a master laser configured to emit master laser pulses at a master clock frequency; focusing the master laser pulses through the back side of the semiconductor into a first P-N junction disposed in the semiconductor; converting a current generated in the first P-N junction in response to the master laser pulses into a clock signal; and clocking a first area of the integrated circuit disposed in the semiconductor.
Claim 23
Independent Claim
94 words
A method for optically clocking an integrated circuit in a semiconductor including at least a front and back side, the method comprising the steps of: operating a master laser configured to emit master laser pulses at a master clock frequency; focusing the master laser pulses through the back side of the semiconductor into a first P-N junction disposed in the semiconductor; converting a current generated in the first P-N junction in response to the master laser pulses into a clock signal; and clocking a first area of the integrated circuit disposed in the semiconductor.
Claim 24
Dependent Claim
32 words
The method described in claim 21 including the additional step of buffering the clock signal after the step of converting the current generated in the first P-N junction in the clock signal.
Claim 25
Dependent Claim
62 words
The method described in claim 21 including the additional step of: splitting the master laser pulses into first and second split laser pulses; wherein the step of focusing the master laser pulses through the back side of the semiconductor includes the step of focusing the first and second split laser pulses into the first P-N junction and a second P-N junction respectively.
Claim 26
Dependent Claim
32 words
The method described in claim 23 wherein the first and second P-N junctions are disposed in the semiconductor, the second split laser pulses being focused through the back side of the semiconductor.
Claim 27
Dependent Claim
32 words
The method described in claim 23 wherein the second P-N junction is disposed in a second semiconductor, the second split laser pulses being focused through a back side of the second semiconductor.
Claim 28
Dependent Claim
46 words
The method described in claim 25 including the additional steps of: converting a current generated in the second P-N junction in response to the second split laser pulses into the clock signal; and clocking a second area of an integrated circuit disposed in the second semiconductor.
Claim 29
Dependent Claim
48 words
The method described in claim 21 including the step of thinning a portion of semiconductor disposed between the first P-N junction and the master laser so as to increase a transmission of the master laser pulses through the back side of the semiconductor into the first P-N junction.
Claim 30
Dependent Claim
101 words
An optical clock distribution network, comprising: first photodetection means disposed in a first semiconductor including at least a front and back side for detecting photons; master laser generation means for generating master laser pulses having photons at a clock frequency, the first photodetection means detecting the master laser pulses through the back side of the first semiconductor; and first clock signal generation means coupled to the first photodetection means for generating a first clock signal in response to the master laser pulses, the first clock signal configured to clock a first area of an integrated circuit disposed in the first semiconductor.
Claim 31
Dependent Claim
101 words
An optical clock distribution network, comprising: first photodetection means disposed in a first semiconductor including at least a front and back side for detecting photons; master laser generation means for generating master laser pulses having photons at a clock frequency, the first photodetection means detecting the master laser pulses through the back side of the first semiconductor; and first clock signal generation means coupled to the first photodetection means for generating a first clock signal in response to the master laser pulses, the first clock signal configured to clock a first area of an integrated circuit disposed in the first semiconductor.
Claim 32
Dependent Claim
69 words
The optical clock distribution network described in claim 28 wherein the first clock signal generation means comprises: first conversion means coupled to the first photodetection means for converting a current signal generated by the first photodetection means to the clock signal; and first buffering means coupled between the first conversion means and the first area of the integrated circuit disposed in the first semiconductor for buffering the clock signal.
Claim 33
Dependent Claim
122 words
The optical clock distribution network described in claim 28 further comprising: second photodetection means disposed in the first semiconductor for detecting photons; optics means disposed between the master laser generation means and the first and second photodetection means for splitting the master laser pulses into first and second split laser pulses, the optics means focusing the first and second split laser pulses through a back side of the first semiconductor into the first and second photodetection means respectively; and second clock signal generation means coupled to the second photodetection means for generating a second clock signal in response to the master laser pulses, the second clock signal configured to clock a second area of the integrated circuit disposed in the first semiconductor.
Claim 34
Dependent Claim
137 words
The optical clock distribution network described in claim 28 further comprising: second photodetection means disposed in a second semiconductor for detecting photons; optics means disposed between the master laser generation means and the first and second photodetection means for splitting the master laser pulses into first and second split laser pulses, the optics means focusing the first split laser pulses through the back side of the first semiconductor into the first photodetection means and focusing the second split laser pulses through a back side of the second semiconductor into the second photodetection means; and second clock signal generation means coupled to the second photodetection means for generating a second clock signal in response to the master laser pulses, the second clock signal configured to clock a second area of an integrated circuit disposed in the second semiconductor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-21 | 2002-03-23 | 2002-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-21 | 2006-03-23 | 2006-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-21 | 2010-03-23 | 2010-09-22 | $7700.00 | Window Closed / Lapsed |