US5508835A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Master clock distributing method and apparatus using same
Assignee: Hitachi Ltd
•
Filing: 1993-09-27
•
Granted: 1996-04-16
•
Expires: 2013-09-27
Abstract
Abstract A logic processing apparatus comprises a plurality of integrated circuits, a multi-phase clock generator for distributing clock signals having different phases from one another to the respective integrated circuits, and a package, for air tight sealing the multi-phase clock generator and the plurality of integrated circuits, which has an optical signal transmissible window for transmitting the master clock signal to the multi-phase clock generator through the optical transmitting line.
Inventors
- 👤 Yasushi Takahashi
- 👤 Hiroyuki Itoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:25
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0075; G; G06; G06F; G06F1/00; G06F1/04; G06F1/06; G06F1/10; G06F1/105; H04L7/02; H04L7/033; H04L7/0337
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
129 words
A method for distributing a master clock signal to a plurality of integrated circuits with predetermined phase differences, comprising the steps of: generating a first optical clock signal as a master clock signal; transmitting the first optical clock signal to a logic processing unit having a plurality of integrated circuits; generating a plurality of second optical clock signals having predetermined phase differences from the first optical clock signal received in said logic processing unit, wherein said step of generating the plurality of second optical clock signals includes the sub-steps of: distributing the first optical clock signal, and delaying the distributed first optical clock signal with different delay times in order to make the second optical clock signals; and distributing said second optical clock signals to the respective integrated circuits.
Claim 2
Independent Claim
129 words
A method for distributing a master clock signal to a plurality of integrated circuits with predetermined phase differences, comprising the steps of: generating a first optical clock signal as a master clock signal; transmitting the first optical clock signal to a logic processing unit having a plurality of integrated circuits; generating a plurality of second optical clock signals having predetermined phase differences from the first optical clock signal received in said logic processing unit, wherein said step of generating the plurality of second optical clock signals includes the sub-steps of: distributing the first optical clock signal, and delaying the distributed first optical clock signal with different delay times in order to make the second optical clock signals; and distributing said second optical clock signals to the respective integrated circuits.
Claim 3
Dependent Claim
153 words
A logic processing apparatus, comprising: a master clock generator generating a first optical clock signal; a first optical transmission line having one end thereof coupled to said master clock generator; and a logic processing unit coupled to the other end of said first optical transmission line, said logic processing unit including: a multi-phase clock generator generating a plurality of second optical clock signals having predetermined phase differences, based on the first optical clock signal, wherein said multi-phase clock generator comprises: an optical branch circuit distributing the first optical clock signal, and a plurality of optical delay lines each delaying the distributed first optical clock signal with a different delay time to make the second optical clock signals, a plurality of second optical transmission lines, each having one end thereof coupled to said multi-phase clock generator, and a plurality of integrated circuits receiving the second optical clock signals through said second optical transmission lines.
Claim 4
Dependent Claim
153 words
A logic processing apparatus, comprising: a master clock generator generating a first optical clock signal; a first optical transmission line having one end thereof coupled to said master clock generator; and a logic processing unit coupled to the other end of said first optical transmission line, said logic processing unit including: a multi-phase clock generator generating a plurality of second optical clock signals having predetermined phase differences, based on the first optical clock signal, wherein said multi-phase clock generator comprises: an optical branch circuit distributing the first optical clock signal, and a plurality of optical delay lines each delaying the distributed first optical clock signal with a different delay time to make the second optical clock signals, a plurality of second optical transmission lines, each having one end thereof coupled to said multi-phase clock generator, and a plurality of integrated circuits receiving the second optical clock signals through said second optical transmission lines.
Claim 5
Dependent Claim
72 words
A logic processing apparatus according to claim 2, wherein at least one of said integrated circuits includes: a plurality of photoelectric converters, first optical guides, each having one end thereof coupled to a respective one of said photoelectric converters and the other end thereof coupled together at a substantially central portion of each integrated circuit, and a second optical guide coupled to the other end of all of said first optical guides.
Claim 6
Dependent Claim
118 words
A logic processing unit, comprising: a multi-phase clock generator inputting a first optical clock signal as a master clock signal and generating a plurality of second optical clock signals having predetermined phase differences based on the first optical clock signal, wherein said multi-phase clock generator comprises: an optical branch circuit distributing the first optical clock signal, and a plurality of optical delay lines each delaying the distributed first optical clock signal with a different delay time to make the second optical clock signals; a plurality of second optical transmission lines, each having one end thereof coupled to said multi-phase generator; and a plurality of integrated circuits receiving the second optical clock signals through said second optical transmission lines.
Claim 7
Dependent Claim
118 words
A logic processing unit, comprising: a multi-phase clock generator inputting a first optical clock signal as a master clock signal and generating a plurality of second optical clock signals having predetermined phase differences based on the first optical clock signal, wherein said multi-phase clock generator comprises: an optical branch circuit distributing the first optical clock signal, and a plurality of optical delay lines each delaying the distributed first optical clock signal with a different delay time to make the second optical clock signals; a plurality of second optical transmission lines, each having one end thereof coupled to said multi-phase generator; and a plurality of integrated circuits receiving the second optical clock signals through said second optical transmission lines.
References Cited (Backward Citations)
US4393515A
Cited
WO1986005939A1
Cited
US4695120A
Cited
WO1987006411A1
Cited
US4911512A
Cited
US4755704A
Cited
JPH01156870A
Cited
US4904036A
Cited
US4977581A
Cited
US5122679A
Cited
US4959540A
Cited
US5077529A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-16 | 1999-10-16 | 2000-04-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-16 | 2003-10-16 | 2004-04-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-16 | 2007-10-16 | 2008-04-16 | $7700.00 | Window Closed / Lapsed |