US4977581A
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US
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Multiple frequency clock system
Assignee: Unisys Corp
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Filing: 1988-08-18
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Granted: 1990-12-11
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Expires: 2008-08-18
Abstract
Abstract A plural clock system for multiple processor configurations is provided which comprises one clock system for each processor. Each pre-synchronized clock system has a strobe unit and multi-phase output generator. Each multi-phase output generator has a strobe input signal, a plurality of phase output signals and an expansion sync output signal. One of the clock systems employs its oscillator as the master oscillator for the master plural clock system and the other pre-synchronized clock systems are coupled to, and synchronized by the expansion sync output signals of other clock systems.
Inventors
- 👤 Dominic Cerminara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:08
CPC Classifications
H; H04; H04L; H04L7/00; G; G06; G06F; G06F1/00; G06F1/04; G06F1/10
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
162 words
A synchronous clock system for multiple processor configurations, comprising: a plurality of clock systems, one for each processor, each providing multi-phase clock output signals, each clock system having its own strobe unit and a multi-phase generator unit, each strobe unit having a sync signal input and a data strobe output, each said multi-phase generator unit having a strobe input, a plurality of phase signal outputs and an expansion sync output, one of said clock systems being the master clock system having a master sync signal input which originates upon a system power ON condition and having a master expansion sync output, and the other ones of said plurality of clock systems being slave clock systems, one of which has its strobe input coupled to the master expansion sync output of said master clock system and the other ones of said slave clock systems each having its strobe input coupled to an expansion sync output of another one of said slave clock systems.
Claim 2
Dependent Claim
162 words
A synchronous clock system for multiple processor configurations, comprising: a plurality of clock systems, one for each processor, each providing multi-phase clock output signals, each clock system having its own strobe unit and a multi-phase generator unit, each strobe unit having a sync signal input and a data strobe output, each said multi-phase generator unit having a strobe input, a plurality of phase signal outputs and an expansion sync output, one of said clock systems being the master clock system having a master sync signal input which originates upon a system power ON condition and having a master expansion sync output, and the other ones of said plurality of clock systems being slave clock systems, one of which has its strobe input coupled to the master expansion sync output of said master clock system and the other ones of said slave clock systems each having its strobe input coupled to an expansion sync output of another one of said slave clock systems.
Claim 3
Dependent Claim
60 words
A clock system as set forth in claim 1 wherein the plurality of clock systems are greater than two, and wherein said master expansion sync output is coupled to the sync signal input of a second clock system and the expansion sync output of said second clock system is coupled to the sync signal input of a third clock system.
Claim 4
Dependent Claim
22 words
A clock system as set forth in claim 2 which further includes master oscillator means coupled to each of said clock systems.
Claim 5
Dependent Claim
37 words
A clock system as set forth in claim 3 wherein said master oscillator means provides output clock signals coupled to the input of said strobe units and to the input and output of said multi-phase generator units.
Claim 6
Dependent Claim
23 words
A clock system as set forth in claim 1 wherein each of said strobe units comprises a plurality of flip-flops coupled in series.
Claim 7
Dependent Claim
20 words
A clock system as set forth in claim 5 wherein said plurality of flip-flops comprises four flip-flops coupled in series.
Claim 8
Dependent Claim
39 words
A clock system as set forth in claim 6 wherein the outputs of the third and fourth flip-flops of said plurality of flip-flops are connected to the input of an AND gate to provide a data strobe signal output.
Claim 9
Dependent Claim
34 words
A clock system as set forth in claim 7 wherein said multi-phase generator unit is provided with an input end around shift register coupled to said data strobe signal output from said strobe unit.
Claim 10
Dependent Claim
35 words
A clock system as set forth in claim 8 wherein said multi-phase generator units further includes an output shift register coupled to said input end around shift register to provide said multi-phase clock output signals.
Claim 11
Dependent Claim
28 words
A clock system as set forth in claim 9 wherein all of the multi-phase clock output signals from said output shift register have the same base frequency output.
Claim 12
Dependent Claim
37 words
A clock system as set forth in claim 9 wherein half of the output multi-phase clock signals are at the same base frequency and the other half of the clock signals are at twice the base frequency.
Claim 13
Dependent Claim
49 words
A clock system as set forth in claim 9 wherein one quarter of the output multi-phase clock signals at the output of said output shift register are the base frequency and one quarter are at twice the base frequency and one quarter are at four times the base frequency.
Claim 14
Dependent Claim
21 words
A clock system as set forth in claim 9 wherein said master oscillator means frequency is between 30 and 50 megahertz.
Claim 15
Dependent Claim
38 words
A clock system as set forth in claim 9 wherein said input and output shift registers of said multi-phase generator unit are coupled through logic OR gates to provide a desired frequency output of said multi-phase clock signals.
Claim 16
Dependent Claim
30 words
A clock system as set forth in claim 4 wherein said master oscillator means is coupled to the output of said multi-phase generator to provide deskewed multi-phase output clock signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-12-10 | 1994-06-11 | 1994-12-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-10 | 1998-06-11 | 1998-12-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-10 | 2002-06-11 | 2002-12-11 | $7700.00 | Window Closed / Lapsed |