Communication intercept device using digital drop receivers in multiple tiers

Claim 2

A communications intercept device, comprising: a) an analog-to-digital converter, having an input for receiving an analog wideband signal, and having an output for transmitting a digitized version of the analog wideband signal; b) a first memory, having an input connected to the output of said analog-to-digital converter for storing the digitized wideband signal, and having an output; c) a first digital drop receiver, having a first input connected to the output of said first memory for selecting signals stored in said first memory, having a second input for receiving a control signal to control what signals are selected from said first memory, and having an output; d) a controller, having an output connected to the second input of said first digital drop receiver for transmitting the control signal to said first digital drop receiver; e) a second memory, having an input connected to the output of said first digital drop receiver for storing the signals selected by said first digital drop receiver, and having an output; and f) a second digital drop receiver, having a first input connected to the output of said second memory for selecting signals stored in said second memory, having a second input connected to the output of said controller for receiving the control signal that controls what signals are selected from said second memory, and having an output at which appears the signals selected by said second digital drop receiver.

Claim 3

The device of claim 1, wherein said analog-to-digital converter is comprised of an analog-to-digital converter that may be operated at less than or equal to 25 MHz.

Claim 4

The device of claim 1, wherein said first memory and said second memory are each comprised of a commercial memory device of sufficient size to store signals of interest.

Claim 5

The device of claim 1, wherein said first digital drop receiver and said second digital drop receiver are each comprised of: a) a numerically controlled oscillator/modulator, having at least one input, having a first output, and having a second output; b) a first decimating digital filter, having an input connected to the first output of said numerically controlled oscillator/modulator; and c) a second decimating digital filter, having an input connected to the second output of said numerically controlled oscillator/modulator, and having an output.

Claim 6

The device of claim 1, wherein said controller is a device selected from the group consisting of a finite state machine and a general purpose microprocessor.

Claim 7

The device of claim 2, wherein said first memory and said second memory are each comprised of a commercial memory device of sufficient size to store signals of interest.

Claim 8

The device of claim 6, wherein said first digital drop receiver and said second digital drop receiver are each comprised of: a) a numerically controlled oscillator/modulator, having at least one input, having a first output, and having a second output; b) a first decimating digital filter, having an input connected to the first output of said numerically controlled oscillator/modulator; and c) a second decimating digital filter, having an input connected to the second output of said numerically controlled oscillator/modulator, and having an output.

Claim 9

The device of claim 7, wherein said controller is a device selected from the group consisting of a finite state machine and a general purpose microprocessor.

Claim 10

A communications intercept device, comprising: a) an analog-to-digital converter, having an input for receiving an analog wideband signal, and having an output for transmitting a digitized version of the analog wideband signal; b) a first plurality of digital drop receivers configured in parallel in a first tier, where each of said first plurality of digital drop receivers has a first input connected to the output of said analog-to-digital converter for selecting signals from the digitized wideband signal, where each of said first plurality of digital drop receivers has a second input for receiving a control signal to control what signals are selected from said analog-to-digital converter, and where each of said first plurality of digital drop receivers has an output; c) a controller, having an output connected to the second input of each of said first plurality of digital drop receivers for transmitting the control signal to each of said first plurality of digital drop receivers; d) a memory, having an input connected to the output of each of said first plurality of digital drop receivers for storing the signals selected by said first plurality of digital drop receivers, and having an output; and e) a second plurality of digital drop receivers configured in parallel in a second tier, where each of said second plurality of digital drop receivers has a first input connected to the output of said memory for selecting signals stored in said memory, where each of said second plurality of digital drop receivers has a second input connected to the output of said controller for receiving a control signal to control what signals are selected from said memory, and where each of said second plurality of digital drop receivers has an output at which appears the signals selected by said second plurality of digital drop receivers.

Claim 11

A communications intercept device, comprising: a) an analog-to-digital converter, having an input for receiving an analog wideband signal, and having an output for transmitting a digitized version of the analog wideband signal; b) a first plurality of digital drop receivers configured in parallel in a first tier, where each of said first plurality of digital drop receivers has a first input connected to the output of said analog-to-digital converter for selecting signals from the digitized wideband signal, where each of said first plurality of digital drop receivers has a second input for receiving a control signal to control what signals are selected from said analog-to-digital converter, and where each of said first plurality of digital drop receivers has an output; c) a controller, having an output connected to the second input of each of said first plurality of digital drop receivers for transmitting the control signal to each of said first plurality of digital drop receivers; d) a memory, having an input connected to the output of each of said first plurality of digital drop receivers for storing the signals selected by said first plurality of digital drop receivers, and having an output; and e) a second plurality of digital drop receivers configured in parallel in a second tier, where each of said second plurality of digital drop receivers has a first input connected to the output of said memory for selecting signals stored in said memory, where each of said second plurality of digital drop receivers has a second input connected to the output of said controller for receiving a control signal to control what signals are selected from said memory, and where each of said second plurality of digital drop receivers has an output at which appears the signals selected by said second plurality of digital drop receivers.

Claim 12

The device of claim 9, wherein said analog-to-digital converter is comprised of an analog-to-digital converter that may be operated at less than or equal to 25 MHz.

Claim 13

The device of claim 9, wherein said memory is comprised of a commercial memory device of sufficient size to store signals of interest.

Claim 14

The device of claim 9, wherein each of said first plurality of digital drop receivers and each of said second plurality of digital drop receivers is comprised of: a) a numerically controlled oscillator/modulator, having at least one input, having a first output, and having a second output; b) a first decimating digital filter, having an input connected to the first output of said numerically controlled oscillator/modulator; and c) a second decimating digital filter, having an input connected to the second output of said numerically controlled oscillator/modulator, and having an output.

Claim 15

The device of claim 9, wherein said controller is a device selected from the group consisting of a finite state machine and a general purpose microprocessor.

Claim 16

The device of claim 10, wherein said memory is comprised of a commercial memory device of sufficient size to store signals of interest.

Claim 17

The device of claim 14, wherein each of said first plurality of digital drop receivers and each of said second plurality of digital drop receivers is comprised of: a) a numerically controlled oscillator/modulator, having at least one input, having a first output, and having a second output; b) a first decimating digital filter, having an input connected to the first output of said numerically controlled oscillator/modulator; and c) a second decimating digital filter, having an input connected to the second output of said numerically controlled oscillator/modulator, and having an output.

Claim 18

The device of claim 15, wherein said controller is a device selected from the group consisting of a finite state machine and a general purpose microprocessor.