US5570392A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase generator
Assignee: Intersil Corp
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Filing: 1995-06-01
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Granted: 1996-10-29
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Expires: 2015-06-01
Abstract
Abstract A digital down converter with a programmable mixing down frequency and a programmable extraction bandwidth uses a ROM based sin/cos generator plus a programmable high decimation filter followed by a gain compensating scaling multiplier and a fixed FIR filter. Output format options are also programmable, and programming commands are serially loaded into registers. Various components may be isolated for efficient testing and also subsystem operation.
Inventors
- 👤 William R. Young
- 👤 David B. Chester
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 21:21
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/0003; H04B1/0007; H04B1/0021; H03; H03D; H03D7/00; H03D7/16; H03D7/165; H03H; H03H17/00; H03H17/02; H03H17/06; H04B1/06; H04B1/16; H04B1/26; H04B1/30; H04J; H04J1/00; H04J1/02; H04J1/04; H04J1/05; H04Q; H04Q11/00; H04Q11/04
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
469 words
A phase generator, comprising: a phase accumulator; a phase increment accumulator coupled to said phase accumulator; a minimum phase increment register coupled to said phase increment accumulator; a maximum phase increment register coupled to said phase increment accumulator; a delta phase increment register coupled to said phase increment accumulator; and a controller intercoupling said accumulators and registers with said phase increment accumulator coupled though a first adder/subtractor to said phase accumulator and with the following modes of coupling: (1) normal mode couples said minimum phase increment register to said phase increment accumulator whereby the contents of said phase accumulator is successively incremented by the contents of said phase increment accumulator which are derived from said minimum phase increment register; (2) chirp up mode couples said minimum phase increment register to said phase increment accumulator, said delta phase increment register through a second adder/subtractor to said phase increment accumulator, and said maximum phase register through a comparator to said phase increment accumulator whereby the contents of said phase accumulator is successively incremented by the contents of said phase increment accumulator which are successively incremented by the contents of said delta phase register from an initial contents equal to the contents of said minimum phase register and repeating until the contents of said phase increment accumulator exceed the contents of samd maximum phase register; (3) chirp down mode couples said maximum phase increment register to said phase increment accumulator, said delta phase increment register through said second adder/subtractor to said phase increment accumulator, and said minimum phase register through a comparator to said phase increment accumulator whereby the contents of said phase accumulator is successively incremented by the contents of said phase increment accumulator which are successively decremented by the contents of said delta phase register from an initial contents equal to the content of said maximum phase register and repeating until the contents of said phase increment accumulator diminish below the contents of said minimum phase register, and (4) chirp up-down mode couples said minimum phase increment register to said phase increment accumulator, said delta phase increment register through said second adder/subtractor to said phase increment accumulator, and both said maximum phase register and said minimum phase register through a comparator to said phase increment accumulator whereby the contents of said phase accumulator may be successively incremented by the contents of said phase increment accumulator which are successively (i) incremented by the contents of said delta phase register from an initial contents equal to the contents of said minimum phase register, and when the contents of said phase increment accumulator exceed the contents of said maximum phase register (ii) decremented by the contents of said delta phase register, and when the contents of said phase increment accumulator are diminished below the contents of said minimum phase register repeating from (i).
Claim 2
Dependent Claim
469 words
A phase generator, comprising: a phase accumulator; a phase increment accumulator coupled to said phase accumulator; a minimum phase increment register coupled to said phase increment accumulator; a maximum phase increment register coupled to said phase increment accumulator; a delta phase increment register coupled to said phase increment accumulator; and a controller intercoupling said accumulators and registers with said phase increment accumulator coupled though a first adder/subtractor to said phase accumulator and with the following modes of coupling: (1) normal mode couples said minimum phase increment register to said phase increment accumulator whereby the contents of said phase accumulator is successively incremented by the contents of said phase increment accumulator which are derived from said minimum phase increment register; (2) chirp up mode couples said minimum phase increment register to said phase increment accumulator, said delta phase increment register through a second adder/subtractor to said phase increment accumulator, and said maximum phase register through a comparator to said phase increment accumulator whereby the contents of said phase accumulator is successively incremented by the contents of said phase increment accumulator which are successively incremented by the contents of said delta phase register from an initial contents equal to the contents of said minimum phase register and repeating until the contents of said phase increment accumulator exceed the contents of samd maximum phase register; (3) chirp down mode couples said maximum phase increment register to said phase increment accumulator, said delta phase increment register through said second adder/subtractor to said phase increment accumulator, and said minimum phase register through a comparator to said phase increment accumulator whereby the contents of said phase accumulator is successively incremented by the contents of said phase increment accumulator which are successively decremented by the contents of said delta phase register from an initial contents equal to the content of said maximum phase register and repeating until the contents of said phase increment accumulator diminish below the contents of said minimum phase register, and (4) chirp up-down mode couples said minimum phase increment register to said phase increment accumulator, said delta phase increment register through said second adder/subtractor to said phase increment accumulator, and both said maximum phase register and said minimum phase register through a comparator to said phase increment accumulator whereby the contents of said phase accumulator may be successively incremented by the contents of said phase increment accumulator which are successively (i) incremented by the contents of said delta phase register from an initial contents equal to the contents of said minimum phase register, and when the contents of said phase increment accumulator exceed the contents of said maximum phase register (ii) decremented by the contents of said delta phase register, and when the contents of said phase increment accumulator are diminished below the contents of said minimum phase register repeating from (i).
Claim 3
Dependent Claim
39 words
The phase generator of claim 1, further comprising: a phase offset register coupled to said phase accumulator by said controller, whereby the initial contents of said phase accumulator is set equal to the contents of said phase offset register.
Claim 4
Dependent Claim
30 words
The phase generator of claim 1, wherein: said controller couples said phase increment accumulator through said first adder/subtractors for decrementing rather than incrementing said the contents of said phase accumulator.
References Cited (Backward Citations)
US4873500A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-29 | 2000-04-29 | 2000-10-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-29 | 2004-04-29 | 2004-10-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-29 | 2008-04-29 | 2008-10-29 | $7700.00 | Window Closed / Lapsed |