Patent US5811345A successfully refreshed from Google Patents.
← Back to Patent Explorer
US5811345A Expired / Lapsed US ⏱️ 0.0 years remaining

Planarization of shallow- trench- isolation without chemical mechanical polishing

Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
•
Filing: 1997-09-18
•
Granted: 1998-09-22
•
Expires: 2017-09-18
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A new method for planarization of shallow trench isolation is disclosed by the wet etching and plasma etching, due to the surface sensitivity of SACVD O 3 -TEOS that depends on substrate. The method described herein includes a pad oxide layer, a silicon nitride layer, and a doped polysilicon oxide layer formed on a silicon substrate. A shallow trench is formed by photolithography and dry etching process to etch the doped polysilicon oxide layer, the silicon nitride layer, the pad oxide layer, and the silicon substrate. A SACVD O 3 -TEOS layer is subsequently formed on the on the doped polysilicon oxide layer and filling into the trench, the deposition rate of the ozone-TEOS layer on the doped polysilicon oxide layer is slower than the deposition rate of the ozone-TEOS layer on the silicon wafer, the wet etching rate of the ozone-TEOS layer on the doped polysilicon oxide layer is faster than the etching rate of the ozone-TEOS layer on the silicon wafer. A wet etching is performed to planarize the ozone-TEOS layer.

Inventors

  • 👤 Chen-Hua Yu
  • 👤 Syun-Ming Jang Jang

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 23:28
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10P95/00; H10P95/06; H10P95/062; H10W10/10; H10W10/17; Y; Y10; Y10S; Y10S438/00; Y10S438/914; Y10S438/916; Y10S438/924

Claims Analysis

Total Claims: 18
Claim 1
Independent Claim 165 words
A method for forming a shallow trench isolation on a silicon wafer, said method comprising the steps of: forming a pad oxide layer on said wafer; forming a silicon nitride layer on said pad layer; forming a doped polysilicon layer on said silicon nitride layer; performing a thermal annealing for converting said doped polysilicon layer into a doped polysilicon oxide layer; forming a trench by etching said doped polysilicon oxide layer, said silicon nitride layer, said pad oxide layer, and said silicon wafer; forming a ozone-TEOS layer for isolation on said doped polysilicon oxide layer and filling into said trench, the deposition rate of said ozone-TEOS layer on said doped polysilicon oxide layer is slower than the deposition rate of said ozone-TEOS layer on said silicon wafer, the wet etching rate of said ozone-TEOS layer on said doped polysilicon oxide layer is faster than the etching rate of said ozone-TEOS layer on said silicon wafer; and performing a wet etching to etch said ozone-TEOS layer.
Claim 2
Independent Claim 165 words
A method for forming a shallow trench isolation on a silicon wafer, said method comprising the steps of: forming a pad oxide layer on said wafer; forming a silicon nitride layer on said pad layer; forming a doped polysilicon layer on said silicon nitride layer; performing a thermal annealing for converting said doped polysilicon layer into a doped polysilicon oxide layer; forming a trench by etching said doped polysilicon oxide layer, said silicon nitride layer, said pad oxide layer, and said silicon wafer; forming a ozone-TEOS layer for isolation on said doped polysilicon oxide layer and filling into said trench, the deposition rate of said ozone-TEOS layer on said doped polysilicon oxide layer is slower than the deposition rate of said ozone-TEOS layer on said silicon wafer, the wet etching rate of said ozone-TEOS layer on said doped polysilicon oxide layer is faster than the etching rate of said ozone-TEOS layer on said silicon wafer; and performing a wet etching to etch said ozone-TEOS layer.
Claim 3
Dependent Claim 14 words
The method of claim 1, wherein said ozone-TEOS layer is formed by sub-atmospheric CVD.
Claim 4
Dependent Claim 24 words
The method of claim 1, wherein said the deposition rate of said ozone-TEOS layer on said silicon wafer is about 1500 to 2000 angstroms/minute.
Claim 5
Dependent Claim 25 words
The method of claim 1, wherein said the deposition rate of said ozone-TEOS layer on said doped-polysilicon oxide layer is about 100 to 150 angstroms/minute.
Claim 6
Dependent Claim 27 words
The method of claim 1, wherein said the wet etching rate of said ozone-TEOS layer on said doped polysilicon oxide layer is about 2000 to 3000 angstroms/minute.
Claim 7
Dependent Claim 25 words
The method of claim 1, wherein said the wet etching rate of said ozone-TEOS layer on said silicon wafer is about 280 to 320 angstroms/minute.
Claim 8
Dependent Claim 15 words
The method of claim 1, wherein the etchant of said wet etching is HF solution.
Claim 9
Dependent Claim 23 words
The method of claim 1, further comprising: performing a plasma etching to remove the remaining said ozone-TEOS layer after performing said wet etching.
Claim 10
Independent Claim 145 words
A method for forming a shallow trench isolation on a silicon wafer, said method comprising the steps of: forming a pad oxide layer on said wafer; forming a silicon nitride layer on said pad layer; forming a plasma-enhanced PSG layer on said silicon nitride layer; forming a trench by etching said plasma-enhanced PSG layer, said silicon nitride layer, said pad oxide layer, and said silicon wafer; forming a ozone-TEOS layer for isolation on said plasma-enhanced PSG layer and filling into said trench, the deposition rate of said ozone-TEOS layer on said plasma-enhanced PSG layer is slower than the deposition rate of said ozone-TEOS layer on said silicon wafer, the etching rate of said ozone-TEOS layer on said plasma-enhanced PSG layer is faster than the etching rate of said ozone-TEOS layer on said silicon wafer; and performing a wet etching process to etch said ozone-TEOS layer.
Claim 11
Independent Claim 145 words
A method for forming a shallow trench isolation on a silicon wafer, said method comprising the steps of: forming a pad oxide layer on said wafer; forming a silicon nitride layer on said pad layer; forming a plasma-enhanced PSG layer on said silicon nitride layer; forming a trench by etching said plasma-enhanced PSG layer, said silicon nitride layer, said pad oxide layer, and said silicon wafer; forming a ozone-TEOS layer for isolation on said plasma-enhanced PSG layer and filling into said trench, the deposition rate of said ozone-TEOS layer on said plasma-enhanced PSG layer is slower than the deposition rate of said ozone-TEOS layer on said silicon wafer, the etching rate of said ozone-TEOS layer on said plasma-enhanced PSG layer is faster than the etching rate of said ozone-TEOS layer on said silicon wafer; and performing a wet etching process to etch said ozone-TEOS layer.
Claim 12
Dependent Claim 14 words
The method of claim 9, wherein said ozone-TEOS layer is formed by sub-atmospheric CVD.
Claim 13
Dependent Claim 24 words
The method of claim 9, wherein said the deposition rate of said ozone-TEOS layer on said silicon wafer is about 1500 to 2000 angstroms/minute.
Claim 14
Dependent Claim 25 words
The method of claim 9, wherein said the deposition rate of said ozone-TEOS layer on said plasma-enhanced PSG layer is about 90 to 130 angstroms/minute.
Claim 15
Dependent Claim 25 words
The method of claim 9, wherein said the wet etching rate of said ozone-TEOS layer on said silicon wafer is about 280 to 320 angstroms/minute.
Claim 16
Dependent Claim 26 words
The method of claim 9, wherein said the wet etching rate of said ozone-TEOS layer on said plasma-enhanced PSG layer is about 2000 to 2500 angstroms/minute.
Claim 17
Dependent Claim 15 words
The method of claim 9, wherein the etchant of said wet etching is HF solution.
Claim 18
Dependent Claim 28 words
The method of claim 9, wherein said wet etching process further comprising: performing a plasma etching to remove the remaining said ozone-TEOS layer after performing said wet etching.

References Cited (Backward Citations)

US3892608A Cited
US4507849A Cited
US5498565A Cited
US5314843A Cited
US5578518A Cited
US5665635A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-09-21 2002-03-23 2002-09-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-09-21 2006-03-23 2006-09-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-09-21 2010-03-23 2010-09-22 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag