Variable gain circuit and radio apparatus using the same

Claim 2

A radio apparatus adapted for receiving data by performing a frequency conversion of a receiving signal from a radio frequency into a base band frequency to perform a predetermined signal processing, said apparatus at least comprising: an input terminal; an output terminal; a plurality of gain stages directly connected in parallel between said input terminal and said output terminal; and signal processing means for controlling a change-over from one of the plurality of gain stages to another of the plurality of gain stages corresponding to said receiving signal of the radio frequency.

Claim 3

The radio apparatus according to claim 1, wherein an input impedance value of one of the plurality of gain stages viewed from said input terminal is substantially equal to another input impedance value of another of the plurality of gain stages connected in parallel.

Claim 4

The radio apparatus according to claim 1, wherein an output impedance value of one of the plurality of gain stages viewed from said output terminal is substantially equal to another output impedance value of another of the plurality of gain stages connected in parallel.

Claim 5

The radio apparatus according to claim 1, wherein an input impedance value of one of the plurality of gain stages viewed from said input terminal is substantially equal to another input impedance value of another of the plurality of gain stages connected in parallel, and an output impedance value of one of the plurality of gain stages viewed from said output terminal is substantially equal to another output impedance value of another of the plurality of gain stages connected in parallel.

Claim 6

The radio apparatus according to claim 1, wherein said radio apparatus further comprises a signal power detection means for detecting signal power of said receiving signal of said radio frequency; and said signal processing means controls said change-over corresponding to said signal power of said receiving signal of the radio frequency.

Claim 7

The radio apparatus according to claim 5, wherein said signal power detection means further comprises an amplitude detection means for detecting an amplitude value of said receiving signal of the radio frequency; and said signal processing means controls said change-over corresponding to said amplitude value of said receiving signal of the radio frequency.

Claim 8

A variable gain circuit comprising: an input terminal; an output terminal; a plurality of gain stages directly connected in parallel between the input terminal and the output terminal; a control unit for allowing said plurality of gain stages to be selectively operative; an input side matching circuit having an input side, an input impedance value viewed from said input side and representing an input impedance of the variable gain circuit, and an output connected in series to said input terminal; and an output side matching circuit having an input connected in series to said output terminal, an output side, and an output impedance value viewed from said output side and representing an output impedance of the variable gain circuit.

Claim 9

A variable gain circuit comprising: an input terminal; an output terminal; a plurality of gain stages directly connected in parallel between the input terminal and the output terminal; a control unit for allowing said plurality of gain stages to be selectively operative; an input side matching circuit having an input side, an input impedance value viewed from said input side and representing an input impedance of the variable gain circuit, and an output connected in series to said input terminal; and an output side matching circuit having an input connected in series to said output terminal, an output side, and an output impedance value viewed from said output side and representing an output impedance of the variable gain circuit.

Claim 10

The variable gain circuit according to claim 7, wherein each of said plurality of gain stages comprises: an input stage for inputting a high frequency signal; at least one amplifier stage, connected in series to said input stage, for outputting an amplified signal; and an output stage, connected in series to said at least one amplifier stage.

Claim 11

The variable gain circuit according to claim 7, wherein the input impedance value is substantially the same regardless of which of the plurality of gain stages are operative.

Claim 12

The variable gain circuit according to claim 7, wherein the output impedance value is substantially the same regardless of which of the plurality of gain stages are operative.

Claim 13

A variable gain circuit comprising: an input terminal; an output terminal; a plurality of gain stages, directly connected in parallel between the input terminal and the output terminal, each having an input stage, at lest one amplifier stage, and an output stage connected in series; and a control unit for allowing said plurality of gain stages to be selectively operative; wherein each output stage of the plurality of gain stages is caused to have substantially the same circuit configuration and substantially the same circuit constants as any other of the plurality of gain stages, such that an input impedance viewed from said input terminal remains substantially the same regardless of which of the plurality of gain stages are operative; and wherein each output stage of the plurality of gain stages is caused to have substantially the same circuit configuration and substantially the same circuit constants as any other of the plurality of gain stages, such that an output impedance viewed from said output terminal remains substantially the same regardless of which of the plurality of gain stages are operative.

Claim 14

A variable gain circuit comprising: an input terminal; an output terminal; a plurality of gain stages, directly connected in parallel between the input terminal and the output terminal, each having an input stage, at lest one amplifier stage, and an output stage connected in series; and a control unit for allowing said plurality of gain stages to be selectively operative; wherein each output stage of the plurality of gain stages is caused to have substantially the same circuit configuration and substantially the same circuit constants as any other of the plurality of gain stages, such that an input impedance viewed from said input terminal remains substantially the same regardless of which of the plurality of gain stages are operative; and wherein each output stage of the plurality of gain stages is caused to have substantially the same circuit configuration and substantially the same circuit constants as any other of the plurality of gain stages, such that an output impedance viewed from said output terminal remains substantially the same regardless of which of the plurality of gain stages are operative.