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US5805902A
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Structure and method for issuing interrupt requests as addresses and for decoding the addresses issued as interrupt requests
Assignee: LG Electronics Inc
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Filing: 1997-10-28
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Granted: 1998-09-08
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Expires: 2017-10-28
Abstract
Abstract An interrupt control circuit for use in a computer system has a CPU, a peripheral I/O device, and a bus having address lines for carrying signals to and from the peripheral I/O device. Interrupt requests generated by the I/O device are encoded as address signals which are transmitted on the address bus lines. A predetermined set of addresses are set aside to represent the interrupt requests. The interrupt control circuit is coupled to the address bus lines to receive the encoded interrupt requests. The interrupt control circuit has an address decoder which receives address signals from the I/O device. When these address signals represent an address within the predetermined set of addresses set aside to represent the interrupt requests, the address decoder uses the address signals to create a plurality of interrupt control signals. The interrupt control signals are provided to an interrupt latch/decoder which uses the interrupt control signals to create interrupt request signals. The interrupt request signals are provided to an interrupt controller. In response, the interrupt controller and the CPU process the interrupt request.
Inventors
- 👤 Dan Kikinis
- 👤 Pascal Dornier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:51
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4221; G06F13/423; F; F02; F02B; F02B75/00; F02B75/02; F02B2075/022; F02B2075/027
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
158 words
A method for issuing and processing interrupt requests in a computer having a central processing unit (CPU) and peripheral I/O devices comprising steps of: (a) reserving a set of addresses in the address space of the computer, individual ones of the reserved addresses representing individual ones of the peripheral devices; (b) issuing interrupt requests from the peripheral I/O devices to an interrupt control circuit as addresses in the reserved set of addresses on an address bus connecting the peripheral I/O devices and the interrupt control circuit; (c) decoding the addresses at the interrupt control circuit to determine the requesting peripheral I/O device; and (d) issuing interrupt signals to the CPU by the interrupt control circuit in response to the decoded addresses; wherein the interrupt control circuit comprises decoders and a conventional interrupt controller, and wherein the decoders provides specific interrupt control signals to the interrupt controller according to the addresses decoded, and the interrupt controller interrupts the CPU.
Claim 2
Independent Claim
158 words
A method for issuing and processing interrupt requests in a computer having a central processing unit (CPU) and peripheral I/O devices comprising steps of: (a) reserving a set of addresses in the address space of the computer, individual ones of the reserved addresses representing individual ones of the peripheral devices; (b) issuing interrupt requests from the peripheral I/O devices to an interrupt control circuit as addresses in the reserved set of addresses on an address bus connecting the peripheral I/O devices and the interrupt control circuit; (c) decoding the addresses at the interrupt control circuit to determine the requesting peripheral I/O device; and (d) issuing interrupt signals to the CPU by the interrupt control circuit in response to the decoded addresses; wherein the interrupt control circuit comprises decoders and a conventional interrupt controller, and wherein the decoders provides specific interrupt control signals to the interrupt controller according to the addresses decoded, and the interrupt controller interrupts the CPU.
Claim 3
Independent Claim
171 words
A method for issuing and processing interrupt requests in a computer having a central processing unit (CPU) and peripheral I/O devices comprising steps of: (a) reserving a set of addresses in the address space of the computer, individual ones of the reserved addresses representing individual ones of the peripheral devices; (b) issuing interrupt requests from the peripheral I/O devices to an interrupt control circuit as addresses in the reserved set of addresses on an address bus connecting the peripheral I/O devices and the interrupt control circuit; (c) decoding the addresses at the interrupt control circuit to determine the requesting peripheral I/O device; and (d) issuing interrupt signals to the CPU by the interrupt control circuit in response to the decoded addresses; (e) issuing an acknowledge signal to the interrupt controller by the CPU in response to the interrupts issued by the interrupt controller; and (f) vectoring the CPU to interrupt service routines particular to the decoded interrupts by the interrupt controller in response to the acknowledge signals issued by the CPU.
Claim 4
Independent Claim
171 words
A method for issuing and processing interrupt requests in a computer having a central processing unit (CPU) and peripheral I/O devices comprising steps of: (a) reserving a set of addresses in the address space of the computer, individual ones of the reserved addresses representing individual ones of the peripheral devices; (b) issuing interrupt requests from the peripheral I/O devices to an interrupt control circuit as addresses in the reserved set of addresses on an address bus connecting the peripheral I/O devices and the interrupt control circuit; (c) decoding the addresses at the interrupt control circuit to determine the requesting peripheral I/O device; and (d) issuing interrupt signals to the CPU by the interrupt control circuit in response to the decoded addresses; (e) issuing an acknowledge signal to the interrupt controller by the CPU in response to the interrupts issued by the interrupt controller; and (f) vectoring the CPU to interrupt service routines particular to the decoded interrupts by the interrupt controller in response to the acknowledge signals issued by the CPU.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-07 | 2002-03-09 | 2002-09-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-07 | 2006-03-09 | 2006-09-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-07 | 2010-03-09 | 2010-09-08 | $7700.00 | Window Closed / Lapsed |