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US5802598A
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Data memory access control and method using fixed size memory sections that are sub-divided into a fixed number of variable size sub-sections
Assignee: ARM Ltd
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Filing: 1995-10-02
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Granted: 1998-09-01
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Expires: 2015-10-02
Abstract
Abstract A data processing system and method include an address space which is controlled by a memory management unit and which is treated as being divided into main-sections (chunks) and sub-sections (grains). The grains may be configured to be of one of a selected number of sizes. Irrespective of the grain size, there is a fixed number of grains within each chunk. A bank of grain registers 20 stores access control parameters for each grain. In operation, a memory address (va 31:0!) is decoded to determine which chunk it relates to so that the grain size for that chunk may be determined. Having determined the grain size, the rest of the address may be decoded to pick out the grain in which the address is located, and then the access control parameters for that grain are recovered.
Inventors
- 👤 Simon Charles Watt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 07:18
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0223; G06F12/0292
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
315 words
Apparatus for processing data, said apparatus comprising: a data memory for storing data words at respective memory addresses with an address space of said data memory; means for generating an access request to a data word stored at a specified memory address within said data memory; and a memory management controller for controlling processing of said access request; wherein said memory management controller divides said address space into a plurality of contiguous, fixed size main-sections, each of said main-sections containing a fixed number of sub-sections with said fixed size and said fixed number being the same for each of said main-sections and sub-section size being constant within said main-section and independently set for each of said main-sections, wherein said sub-sections within said main-section are contiguous and said sub-sections are non-contiguous between said main-sections; said memory management controller stores one or more variable access control parameters for each of said sub-sections, said variable access control parameters for each of said sub-sections being used by said memory management controller to control processing of an access request to a specified memory address within each said sub-section; said memory management controller includes a plurality of sub-section registers each storing said one or more access control parameters for a respective sub-section; and said specified memory address includes one or more main-section bits, said main-section bits having a fixed position within said specified memory address, and said main-section bits define said main-section within said address space that contains said specified memory address, said specified memory address includes one or more sub-section bits, said sub-section bits having a bit position within said specified memory address that varies with sub-section size, said sub-section bits define a sub-section within said main-section that contains said specified memory address and said sub-section registers are addressed to read said access control parameters for said specified memory address in response to said main-section bits and said sub-section bits.
Claim 2
Dependent Claim
315 words
Apparatus for processing data, said apparatus comprising: a data memory for storing data words at respective memory addresses with an address space of said data memory; means for generating an access request to a data word stored at a specified memory address within said data memory; and a memory management controller for controlling processing of said access request; wherein said memory management controller divides said address space into a plurality of contiguous, fixed size main-sections, each of said main-sections containing a fixed number of sub-sections with said fixed size and said fixed number being the same for each of said main-sections and sub-section size being constant within said main-section and independently set for each of said main-sections, wherein said sub-sections within said main-section are contiguous and said sub-sections are non-contiguous between said main-sections; said memory management controller stores one or more variable access control parameters for each of said sub-sections, said variable access control parameters for each of said sub-sections being used by said memory management controller to control processing of an access request to a specified memory address within each said sub-section; said memory management controller includes a plurality of sub-section registers each storing said one or more access control parameters for a respective sub-section; and said specified memory address includes one or more main-section bits, said main-section bits having a fixed position within said specified memory address, and said main-section bits define said main-section within said address space that contains said specified memory address, said specified memory address includes one or more sub-section bits, said sub-section bits having a bit position within said specified memory address that varies with sub-section size, said sub-section bits define a sub-section within said main-section that contains said specified memory address and said sub-section registers are addressed to read said access control parameters for said specified memory address in response to said main-section bits and said sub-section bits.
Claim 3
Dependent Claim
23 words
Apparatus as claimed in claim 1, comprising a plurality of main-section registers each storing data defining sub-section size for a respective said main-section.
Claim 4
Dependent Claim
22 words
Apparatus as claimed in claim 2, wherein said data defining sub-section size is written to said main-section registers under program instruction control.
Claim 5
Dependent Claim
29 words
Apparatus as claimed in claim 3, comprising a coprocessor to said central processing unit core, said main-section registers being written under control of program instructions executed by said coprocessor.
Claim 6
Dependent Claim
20 words
Apparatus as claimed in claim 1, wherein said means for generating an access request comprises a central processing unit core.
Claim 7
Dependent Claim
46 words
Apparatus as claimed in claim 1, wherein said specified memory address includes one or more main-section bits, said main-section bits having a fixed position within said specified memory address, and said main-section bits define a main-section within said address space that contains said specified memory address.
Claim 8
Dependent Claim
49 words
Apparatus as claimed in claim 1, wherein said specified memory address includes one or more sub-section bits, said sub-section bits having a bit position within said specified memory address that varies within sub-section size, said sub-section bits define a sub-section within a main-section that contains said specified memory address.
Claim 9
Dependent Claim
36 words
Apparatus as claimed in claim 7, comprising a barrel shifter for selecting said sub-section bits for decoding from within said specified memory address in dependence upon sub-section size for a main-section containing said specified memory address.
Claim 10
Dependent Claim
24 words
Apparatus as claimed in claim 1, wherein said one or more access control parameters are written to said sub-section registers under program instruction control.
Claim 11
Dependent Claim
38 words
Apparatus as claimed in claim 9, wherein said means for generating an access request comprises a central processing unit core and said sub-section registers are written under control of program instructions executed by said central processing unit core.
Claim 12
Dependent Claim
25 words
Apparatus as claimed in claim 1, comprising an abort signal generator for detecting an access request to a specified memory address outside of any sub-section.
Claim 13
Dependent Claim
141 words
Apparatus as claimed in claim 11, wherein said specified memory address includes one or more main-section bits, said main-section bits having a fixed position within said specified memory address, and said main-section bits define a main-section within said address space that contains said specified memory address, said specified memory address includes one or more sub-section bits, said sub-section bits having a bit position within said specified memory address that varies within sub-section size, said sub-section bits define a sub-section within a main-section that contains said specified memory address and said main-section bits are the most significant bits of said specified memory address and said sub-section bits are less significant bits of said specified memory address, said abort signal generator generating an abort signal if any bits of said specified memory address between said main-section bits and said sub-section bits are set.
Claim 14
Dependent Claim
34 words
Apparatus as claimed in claim 11, wherein one or more of said main-sections are reserved, said abort signal generator generating an abort signal if said specified memory address lies within a reserved said main-section.
Claim 15
Dependent Claim
37 words
Apparatus as claimed in claim 1, comprising a write buffer, said one or more access control parameters including a flag indicating whether a write request to said specified memory address may be routed via said write buffer.
Claim 16
Dependent Claim
37 words
Apparatus as claimed in claim 1, comprising a cache memory, said one or more access control parameters including a flag indicating whether a write request to said specified memory address may be written in said cache memory.
Claim 17
Dependent Claim
49 words
Apparatus as claimed in claim 1, wherein said one or more access control parameters include one or more flags that are logically combined with one or more mode bits indicating a current processing mode of said apparatus to determine if said access request is to be permitted to proceed.
Claim 18
Dependent Claim
12 words
Apparatus as claimed in claim 1, said apparatus being an integrated circuit.
Claim 19
Independent Claim
326 words
A method of data processing for operation with a data memory and a memory management controller, said method comprising the steps of: storing data words at respective memory addresses within an address space of the data memory; generating an access request to a data word stored at a specified memory address within said data memory; and controlling processing of said access request with the memory management controller; wherein said memory management controller divides said address space into a plurality of contiguous, fixed size main sections, each of said main-sections containing a fixed number of sub-sections with said fixed size and said fixed number being the same for each of said main-sections and sub-section size being constant within said main-section and independently set for each of said main-sections, wherein said sub-sections within said main-section are contiguous and said sub-sections are non-contiguous between said main-sections; said memory management controller stores one or more variable access control parameters for each of said sub-sections, said variable access control parameters for each of said sub-sections being used by said memory management controller to control processing of an access request to a specified memory address within each said sub-section; and said memory management controller includes a plurality of sub-section registers each storing said one or more access control parameters for a respective sub-section; and said specified memory address includes one or more main-section bits, said main-section bits having a fixed position within said specified memory address, and said main-section bits define said main-section within said address space that contains said specified memory address, said specified memory address includes one or more sub-section bits, said sub-section bits having a bit position within said specified memory address that varies with sub-section size, said sub-section bits define a sub-section within said main-section that contains said specified memory address and said sub-section registers are addressed to read said access control parameters for said specified memory address in response to said main-section bits and said sub-section bits.
Claim 20
Independent Claim
326 words
A method of data processing for operation with a data memory and a memory management controller, said method comprising the steps of: storing data words at respective memory addresses within an address space of the data memory; generating an access request to a data word stored at a specified memory address within said data memory; and controlling processing of said access request with the memory management controller; wherein said memory management controller divides said address space into a plurality of contiguous, fixed size main sections, each of said main-sections containing a fixed number of sub-sections with said fixed size and said fixed number being the same for each of said main-sections and sub-section size being constant within said main-section and independently set for each of said main-sections, wherein said sub-sections within said main-section are contiguous and said sub-sections are non-contiguous between said main-sections; said memory management controller stores one or more variable access control parameters for each of said sub-sections, said variable access control parameters for each of said sub-sections being used by said memory management controller to control processing of an access request to a specified memory address within each said sub-section; and said memory management controller includes a plurality of sub-section registers each storing said one or more access control parameters for a respective sub-section; and said specified memory address includes one or more main-section bits, said main-section bits having a fixed position within said specified memory address, and said main-section bits define said main-section within said address space that contains said specified memory address, said specified memory address includes one or more sub-section bits, said sub-section bits having a bit position within said specified memory address that varies with sub-section size, said sub-section bits define a sub-section within said main-section that contains said specified memory address and said sub-section registers are addressed to read said access control parameters for said specified memory address in response to said main-section bits and said sub-section bits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-31 | 2002-03-02 | 2002-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-31 | 2006-03-02 | 2006-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-31 | 2010-03-02 | 2010-09-01 | $7700.00 | Window Closed / Lapsed |