US5509133A
Expired / Lapsed
US
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Data processing system with an enhanced cache memory control
Assignee: Hitachi Microcomputer System Ltd
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Filing: 1995-05-05
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Granted: 1996-04-16
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Expires: 2015-05-05
Abstract
Abstract A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) is for a part (such as a status register in the above-mentioned microcomputer system) accessible by another procesing device, such as an I/O device, within the entire storage area (such as a main storage and the status register) accessible by the central processing system. If data to be fetched for an instruction executed by the central processing unit is not found in a cache memory, the data is fetched from the entire storage area. A write circuit is provided which writes the fetched data into the cache memory when the detect circuit shows that the access address is not for the part accessible by the other processing device within the entire storage area, but otherwise the write circuit does not write the fetched data into the cache memory.
Inventors
- 👤 Tadahiko Nishimukai
- 👤 Atsushi Hasegawa
- 👤 Masaru Matsumura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 04:48
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3004; G06F9/30043; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0888
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
119 words
A data processing system comprising: a central processing unit executing an instruction and generating logical addresses; a memory management unit converting a logical address received from said central processing unit into a physical address; a bus receiving a physical address from said memory management unit; a memory device; a cache memory coupled to said central processing unit and storing data read from said memory device; and a control circuit coupled to said bus, which receives a physical address from said memory management unit through said bus and inhibits an operation of writing data read from said memory device into said cache memory when a predetermined address of said memory device is accessed by said physical address from said bus.
Claim 2
Dependent Claim
119 words
A data processing system comprising: a central processing unit executing an instruction and generating logical addresses; a memory management unit converting a logical address received from said central processing unit into a physical address; a bus receiving a physical address from said memory management unit; a memory device; a cache memory coupled to said central processing unit and storing data read from said memory device; and a control circuit coupled to said bus, which receives a physical address from said memory management unit through said bus and inhibits an operation of writing data read from said memory device into said cache memory when a predetermined address of said memory device is accessed by said physical address from said bus.
Claim 3
Dependent Claim
23 words
A data processing system according to claim 1, wherein said predetermined address is for communicating a message between processors in a multi-processor system.
Claim 4
Dependent Claim
22 words
A data processing system according to claim 1, wherein said memory device is a shared memory between processors in a multi-processor system.
Claim 5
Dependent Claim
64 words
A data processing system according to claim 1, wherein said control circuit includes: a control signal generator receiving the physical address from said memory management unit and generating a control signal when a predetermined address of said memory device is accessed by said physical address from said bus; and a cache memory control circuit inhibiting the writing operation in response to the control signal.
Claim 6
Dependent Claim
18 words
A data processing system according to claim 1, further comprising: an input/output control device coupled to said bus.
Claim 7
Dependent Claim
118 words
A data processing system comprising: a central processing unit executing an instruction and generating logical addresses; a memory management unit converting a logical address received from said central processing unit into a physical address; a memory device; a cache memory coupled to said central processing unit and storing data read from said memory device; a signal generating circuit receiving a physical address from said memory management unit and generating a control signal when a predetermined address of said memory device is accessed by said physical address from said memory management unit; and a cache memory control circuit inhibiting an operation of writing data read from said memory device into said cache memory in response to the control signal.
Claim 8
Dependent Claim
118 words
A data processing system comprising: a central processing unit executing an instruction and generating logical addresses; a memory management unit converting a logical address received from said central processing unit into a physical address; a memory device; a cache memory coupled to said central processing unit and storing data read from said memory device; a signal generating circuit receiving a physical address from said memory management unit and generating a control signal when a predetermined address of said memory device is accessed by said physical address from said memory management unit; and a cache memory control circuit inhibiting an operation of writing data read from said memory device into said cache memory in response to the control signal.
Claim 9
Dependent Claim
32 words
A data processing system according to claim 6, further comprising: a bus coupled to said memory management unit; wherein said signal generating circuit is coupled between said bus and said memory device.
Claim 10
Dependent Claim
18 words
A data processing system according to claim 7, further comprising: an input/output control device coupled to said bus.
Claim 11
Dependent Claim
23 words
A data processing system according to claim 6, wherein said predetermined address is for communicating a message between processors in a multi-processor system.
Claim 12
Dependent Claim
22 words
A data processing system according to claim 6, wherein said memory device is a shared memory between processors in a multi-processor system.
Claim 13
Dependent Claim
127 words
A data processing system comprising: a central processing unit generating logical addresses; a memory management unit converting a logical address received from said central processing unit into a physical address; a bus receiving a physical address from said memory management unit; a memory; a circuit changing data in said memory independently of said central processing unit; a cache memory coupled to said central processing unit and storing data from said memory; and a control circuit receiving a physical address from said memory management unit and inhibiting an operation of writing data from said memory into said cache memory when a memory region of said memory, which is shared by said circuit and said central processing unit, is accessed by said physical address from said memory management unit.
Claim 14
Dependent Claim
127 words
A data processing system comprising: a central processing unit generating logical addresses; a memory management unit converting a logical address received from said central processing unit into a physical address; a bus receiving a physical address from said memory management unit; a memory; a circuit changing data in said memory independently of said central processing unit; a cache memory coupled to said central processing unit and storing data from said memory; and a control circuit receiving a physical address from said memory management unit and inhibiting an operation of writing data from said memory into said cache memory when a memory region of said memory, which is shared by said circuit and said central processing unit, is accessed by said physical address from said memory management unit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-16 | 1999-10-16 | 2000-04-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-16 | 2003-10-16 | 2004-04-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-16 | 2007-10-16 | 2008-04-16 | $7700.00 | Window Closed / Lapsed |